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Message-ID: <e1df8097-dd48-4570-8f8e-c6c25a3683a4@lunn.ch> Date: Sat, 5 Jul 2025 10:10:40 +0200 From: Andrew Lunn <andrew@...n.ch> To: Sebastian Reichel <sebastian.reichel@...labora.com> Cc: Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Florian Fainelli <florian.fainelli@...adcom.com>, Detlev Casanova <detlev.casanova@...labora.com>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org, stable@...r.kernel.org Subject: Re: [PATCH net] net: phy: realtek: Reset after clock enable On Fri, Jul 04, 2025 at 07:48:44PM +0200, Sebastian Reichel wrote: > On Radxa ROCK 4D boards we are seeing some issues with PHY detection and > stability (e.g. link loss, or not capable of transceiving packages) > after new board revisions switched from a dedicated crystal to providing > the 25 MHz PHY input clock from the SoC instead. > > This board is using a RTL8211F PHY, which is connected to an always-on > regulator. Unfortunately the datasheet does not explicitly mention the > power-up sequence regarding the clock, but it seems to assume that the > clock is always-on (i.e. dedicated crystal). > > By doing an explicit reset after enabling the clock, the issue on the > boards could no longer be observed. I don't know if it helps in this situation, but look at PHY_RST_AFTER_CLK_EN. If it does not actually help, it might be worth mentioning it in the commit message to stop reviewers saying you should see if it is useful. Andrew
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