netdev - Re: [PATCH v2] net: stmmac: Fix interrupt handling for level-triggered mode in DWC

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Message-Id: 
 <175202461300.186229.18400851039185559146.git-patchwork-notify@kernel.org>
Date: Wed, 09 Jul 2025 01:30:13 +0000
From: patchwork-bot+netdevbpf@...nel.org
To: EricChan <chenchuangyu@...omi.com>
Cc: andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
 kuba@...nel.org, pabeni@...hat.com, mcoquelin.stm32@...il.com,
 alexandre.torgue@...s.st.com, fancer.lancer@...il.com,
 guyinggang@...ngson.cn, chenhuacai@...nel.org, si.yanteng@...ux.dev,
 netdev@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
 linux-arm-kernel@...ts.infradead.org, xiaojianfeng1@...omi.com,
 xiongliang@...omi.com
Subject: Re: [PATCH v2] net: stmmac: Fix interrupt handling for
 level-triggered
 mode in DWC_XGMAC2

Hello:

This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@...nel.org>:

On Thu, 3 Jul 2025 10:04:49 +0800 you wrote:
> According to the Synopsys Controller IP XGMAC-10G Ethernet MAC Databook
> v3.30a (section 2.7.2), when the INTM bit in the DMA_Mode register is set
> to 2, the sbd_perch_tx_intr_o[] and sbd_perch_rx_intr_o[] signals operate
> in level-triggered mode. However, in this configuration, the DMA does not
> assert the XGMAC_NIS status bit for Rx or Tx interrupt events.
> 
> This creates a functional regression where the condition
> if (likely(intr_status & XGMAC_NIS)) in dwxgmac2_dma_interrupt() will
> never evaluate to true, preventing proper interrupt handling for
> level-triggered mode. The hardware specification explicitly states that
> "The DMA does not assert the NIS status bit for the Rx or Tx interrupt
> events" (Synopsys DWC_XGMAC2 Databook v3.30a, sec. 2.7.2).
> 
> [...]

Here is the summary with links:
  - [v2] net: stmmac: Fix interrupt handling for level-triggered mode in DWC_XGMAC2
    https://git.kernel.org/netdev/net/c/78b7920a0335

You are awesome, thank you!
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