netdev - Re: [PATCH v2] net: stmmac: Fix interrupt handling for level-triggered mode in DWC

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Message-ID: <20250704183534.GA356576@horms.kernel.org>
Date: Fri, 4 Jul 2025 19:35:34 +0100
From: Simon Horman <horms@...nel.org>
To: EricChan <chenchuangyu@...omi.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>, davem@...emloft.net,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Maxime Coquelin <mcoquelin.stm32@...il.com>,
	Alexandre Torgue <alexandre.torgue@...s.st.com>,
	Serge Semin <fancer.lancer@...il.com>,
	Yinggang Gu <guyinggang@...ngson.cn>,
	Huacai Chen <chenhuacai@...nel.org>,
	Yanteng Si <si.yanteng@...ux.dev>, netdev@...r.kernel.org,
	linux-stm32@...md-mailman.stormreply.com,
	linux-arm-kernel@...ts.infradead.org,
	xiaojianfeng <xiaojianfeng1@...omi.com>,
	xiongliang <xiongliang@...omi.com>
Subject: Re: [PATCH v2] net: stmmac: Fix interrupt handling for
 level-triggered mode in DWC_XGMAC2

On Thu, Jul 03, 2025 at 10:04:49AM +0800, EricChan wrote:
> According to the Synopsys Controller IP XGMAC-10G Ethernet MAC Databook
> v3.30a (section 2.7.2), when the INTM bit in the DMA_Mode register is set
> to 2, the sbd_perch_tx_intr_o[] and sbd_perch_rx_intr_o[] signals operate
> in level-triggered mode. However, in this configuration, the DMA does not
> assert the XGMAC_NIS status bit for Rx or Tx interrupt events.
> 
> This creates a functional regression where the condition
> if (likely(intr_status & XGMAC_NIS)) in dwxgmac2_dma_interrupt() will
> never evaluate to true, preventing proper interrupt handling for
> level-triggered mode. The hardware specification explicitly states that
> "The DMA does not assert the NIS status bit for the Rx or Tx interrupt
> events" (Synopsys DWC_XGMAC2 Databook v3.30a, sec. 2.7.2).
> 
> The fix ensures correct handling of both edge and level-triggered
> interrupts while maintaining backward compatibility with existing
> configurations. It has been tested on the hardware device (not publicly
> available), and it can properly trigger the RX and TX interrupt handling
> in both the INTM=0 and INTM=2 configurations.
> 
> Fixes: d6ddfacd95c7 ("net: stmmac: Add DMA related callbacks for XGMAC2")
> Tested-by: EricChan <chenchuangyu@...omi.com>
> Signed-off-by: EricChan <chenchuangyu@...omi.com>
> ---
> Changes from v1:
> - Add a Fixes tag pointing to the commit in which the problem was introduced
> - Add the testing results of this patch
> 
> [v1] https://lore.kernel.org/all/20250625025134.97056-1-chenchuangyu@xiaomi.com/

Thanks,

I note that this addresses the review by Jakub of v1.

Reviewed-by: Simon Horman <horms@...nel.org>