netdev - RE: [Intel-wired-lan] [PATCH v8 iwl-next] ice: add recovery clock and clock 1588 control for E825c

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Message-ID: <IA3PR11MB898644529A711CF9228CB65DE55EA@IA3PR11MB8986.namprd11.prod.outlook.com>
Date: Thu, 24 Jul 2025 13:44:00 +0000
From: "Loktionov, Aleksandr" <aleksandr.loktionov@...el.com>
To: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>,
	"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Kubalewski, Arkadiusz"
	<arkadiusz.kubalewski@...el.com>, "Korba, Przemyslaw"
	<przemyslaw.korba@...el.com>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>, "Olech, Milena" <milena.olech@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH v8 iwl-next] ice: add recovery clock and
 clock 1588 control for E825c



> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf
> Of Grzegorz Nitka
> Sent: Thursday, July 24, 2025 2:28 PM
> To: intel-wired-lan@...ts.osuosl.org
> Cc: netdev@...r.kernel.org; Kubalewski, Arkadiusz
> <arkadiusz.kubalewski@...el.com>; Korba, Przemyslaw
> <przemyslaw.korba@...el.com>; Nguyen, Anthony L
> <anthony.l.nguyen@...el.com>; Kitszel, Przemyslaw
> <przemyslaw.kitszel@...el.com>; Olech, Milena <milena.olech@...el.com>
> Subject: [Intel-wired-lan] [PATCH v8 iwl-next] ice: add recovery clock
> and clock 1588 control for E825c
> 
> From: Przemyslaw Korba <przemyslaw.korba@...el.com>
> 
> Add control for E825 input pins: phy clock recovery and clock 1588.
> E825 does not provide control over platform level DPLL but it provides
> control over PHY clock recovery, and PTP/timestamp driven inputs for
> platform level DPLL.
> 
> Introduce a software controlled layer of abstraction to:
> - create a DPLL of type EEC for E825c,
> - create recovered clock pin for each PF, and control them through
> writing to registers,
> - create pin to control clock 1588 for PF0, and control it through
> writing to registers.
> 
> Usage example:
> - to get EEC PLL info
> $ ynl --family dpll --dump device-get
> [{'clock-id': 0,
>   'id': 6,
>   'lock-status': 'locked',
>   'mode': 'manual',
>   'mode-supported': ['manual'],
>   'module-name': 'ice',
>   'type': 'eec'},
> ...
>   ]
> 
> - to get 1588 and rclk pins info
> (note: in the output below, pin id=31 is a representor for 1588 input,
> while pins 32..35 corresponds to PHY clock inputs to SyncE  module) $
> ynl --family dpll --dump pin-get
> [{'board-label': 'CLK_IN_0',
>   'capabilities': set(),
>   'clock-id': 0,
>   'id': 27,
>   'module-name': 'ice',
>   'parent-device': [{'direction': 'input',
>                      'parent-id': 6,
>                      'state': 'connected'}],
>   'phase-adjust-max': 0,
>   'phase-adjust-min': 0,
>   'type': 'mux'},
>  {'board-label': 'CLK_IN_1',
>   'capabilities': set(),
>   'clock-id': 0,
>   'id': 28,
>   'module-name': 'ice',
>   'parent-device': [{'direction': 'input',
>                      'parent-id': 6,
>                      'state': 'connected'}],
>   'phase-adjust-max': 0,
>   'phase-adjust-min': 0,
>   'type': 'mux'},
>  {'board-label': 'pin_1588',
>   'capabilities': {'state-can-change'},
>   'clock-id': 0,
>   'id': 31,
>   'module-name': 'ice',
>   'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
>                  {'parent-id': 28, 'state': 'disconnected'}],
>   'phase-adjust-max': 0,
>   'phase-adjust-min': 0,
>   'type': 'synce-eth-port'},
>  {'capabilities': {'state-can-change'},
>   'clock-id': 0,
>   'id': 32,
>   'module-name': 'ice',
>   'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
>                  {'parent-id': 28, 'state': 'disconnected'}],
>   'phase-adjust-max': 0,
>   'phase-adjust-min': 0,
>   'type': 'synce-eth-port'},
>  {'capabilities': {'state-can-change'},
>   'clock-id': 0,
>   'id': 33,
>   'module-name': 'ice',
>   'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
>                  {'parent-id': 28, 'state': 'disconnected'}],
>   'phase-adjust-max': 0,
>   'phase-adjust-min': 0,
>   'type': 'synce-eth-port'},
>  {'capabilities': {'state-can-change'},
>   'clock-id': 0,
>   'id': 34,
>   'module-name': 'ice',
>   'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
>                  {'parent-id': 28, 'state': 'disconnected'}],
>   'phase-adjust-max': 0,
>   'phase-adjust-min': 0,
>   'type': 'synce-eth-port'},
>  {'capabilities': {'state-can-change'},
>   'clock-id': 0,
>   'id': 35,
>   'module-name': 'ice',
>   'parent-pin': [{'parent-id': 27, 'state': 'disconnected'},
>                  {'parent-id': 28, 'state': 'disconnected'}],
>   'phase-adjust-max': 0,
>   'phase-adjust-min': 0,
>   'type': 'synce-eth-port'}]
> 
> - to set PHY0 clock as SyncE module input $ ynl --family dpll --do
> pin-set --json '{"id":32,"parent-pin":\
>     {"parent-id":27, "state":"connected"}}'
> 
> - to set 1588 Main Timer as source into SyncE module $ ynl --family
> dpll --do pin-set --json '{"id":31,"parent-pin":\
>     {"parent-id":27, "state":"connected"}}'
> 
> Reviewed-by: Milena Olech <milena.olech@...el.com>
> Co-developed-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> Signed-off-by: Przemyslaw Korba <przemyslaw.korba@...el.com>
Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@...el.com>

> ---
> v7->v8:
> - rebased
> - removed unrelated changes
> - change pin_1588 type to DPLL_PIN_TYPE_EXT
> - use ICE_SYNCE_CLK_NUM to determine the number of rclk pins
> ---
... 
> base-commit: c4da238c4a0f62bbaa055f9d85559164df82bd07
> --
> 2.39.3