netdev - Re: [PATCH net v2] net: phy: realtek: Reset after clock enable

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Message-ID: <660d1cf3-1bd2-416a-b5ac-8dc87a87b4e4@broadcom.com>
Date: Thu, 24 Jul 2025 09:09:32 -0700
From: Florian Fainelli <florian.fainelli@...adcom.com>
To: Sebastian Reichel <sebastian.reichel@...labora.com>,
 Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
 Russell King <linux@...linux.org.uk>
Cc: "David S. Miller" <davem@...emloft.net>,
 Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>,
 Paolo Abeni <pabeni@...hat.com>,
 Detlev Casanova <detlev.casanova@...labora.com>, netdev@...r.kernel.org,
 linux-kernel@...r.kernel.org, kernel@...labora.com, stable@...r.kernel.org
Subject: Re: [PATCH net v2] net: phy: realtek: Reset after clock enable

On 7/24/25 07:39, Sebastian Reichel wrote:
> On Radxa ROCK 4D boards we are seeing some issues with PHY detection and
> stability (e.g. link loss or not capable of transceiving packages) after
> new board revisions switched from a dedicated crystal to providing the
> 25 MHz PHY input clock from the SoC instead.
> 
> This board is using a RTL8211F PHY, which is connected to an always-on
> regulator. Unfortunately the datasheet does not explicitly mention the
> power-up sequence regarding the clock, but it seems to assume that the
> clock is always-on (i.e. dedicated crystal).
> 
> By doing an explicit reset after enabling the clock, the issue on the
> boards could no longer be observed.
> 
> Note, that the RK3576 SoC used by the ROCK 4D board does not yet
> support system level PM, so the resume path has not been tested.
> 
> Cc: stable@...r.kernel.org
> Fixes: 7300c9b574cc ("net: phy: realtek: Add optional external PHY clock")
> Signed-off-by: Sebastian Reichel <sebastian.reichel@...labora.com>

Reviewed-by: Florian Fainelli <florian.fainelli@...adcom.com>

Hoping this does not regress other Ethernet controllers and boards in 
the process...
-- 
Florian