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Message-Id: <20250728064938.275304-1-mwalle@kernel.org>
Date: Mon, 28 Jul 2025 08:49:38 +0200
From: Michael Walle <mwalle@...nel.org>
To: Andrew Lunn <andrew+netdev@...n.ch>,
	"David S . Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>,
	Paolo Abeni <pabeni@...hat.com>
Cc: Roger Quadros <rogerq@...nel.org>,
	Simon Horman <horms@...nel.org>,
	Siddharth Vadapalli <s-vadapalli@...com>,
	Matthias Schiffer <matthias.schiffer@...tq-group.com>,
	Maxime Chevallier <maxime.chevallier@...tlin.com>,
	netdev@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Michael Walle <mwalle@...nel.org>
Subject: [PATCH net-next] Revert "net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay"

This reverts commit ca13b249f291f4920466638d1adbfb3f9c8db6e9.

This patch breaks the transmit path on an AM67A/J722S. This SoC has an
(undocumented) configurable delay (CTRL_MMR0_CFG0_ENET1_CTRL, bit 4).

The u-boot driver (net/ti/am65-cpsw-nuss.c) will configure the delay in
am65_cpsw_gmii_sel_k3(). If the u-boot device tree uses rgmii-id this
patch will break the transmit path because it will disable the PHY delay
on the transmit path, but the bootloader has already disabled the MAC
delay, hence there will be no delay at all.

Although the datasheet reads the delay is fixed, that is at least
wrong for the J722S/AM67A and apparently for at least the AM65x
(which was the original target of the u-boot driver).

Fixes: ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
Signed-off-by: Michael Walle <mwalle@...nel.org>
---
This is targeted as net-next although the merge window is open, because
the original patch is just in net-next.
---
 drivers/net/ethernet/ti/am65-cpsw-nuss.c | 27 ++----------------------
 1 file changed, 2 insertions(+), 25 deletions(-)

diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index ecd6ecac87bb..231ca141331f 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -2600,7 +2600,6 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
 		return -ENOENT;
 
 	for_each_child_of_node(node, port_np) {
-		phy_interface_t phy_if;
 		struct am65_cpsw_port *port;
 		u32 port_id;
 
@@ -2666,36 +2665,14 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
 
 		/* get phy/link info */
 		port->slave.port_np = of_node_get(port_np);
-		ret = of_get_phy_mode(port_np, &phy_if);
+		ret = of_get_phy_mode(port_np, &port->slave.phy_if);
 		if (ret) {
 			dev_err(dev, "%pOF read phy-mode err %d\n",
 				port_np, ret);
 			goto of_node_put;
 		}
 
-		/* CPSW controllers supported by this driver have a fixed
-		 * internal TX delay in RGMII mode. Fix up PHY mode to account
-		 * for this and warn about Device Trees that claim to have a TX
-		 * delay on the PCB.
-		 */
-		switch (phy_if) {
-		case PHY_INTERFACE_MODE_RGMII_ID:
-			phy_if = PHY_INTERFACE_MODE_RGMII_RXID;
-			break;
-		case PHY_INTERFACE_MODE_RGMII_TXID:
-			phy_if = PHY_INTERFACE_MODE_RGMII;
-			break;
-		case PHY_INTERFACE_MODE_RGMII:
-		case PHY_INTERFACE_MODE_RGMII_RXID:
-			dev_warn(dev,
-				 "RGMII mode without internal TX delay unsupported; please fix your Device Tree\n");
-			break;
-		default:
-			break;
-		}
-
-		port->slave.phy_if = phy_if;
-		ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, phy_if);
+		ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if);
 		if (ret)
 			goto of_node_put;
 
-- 
2.39.5


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