netdev - Re: [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset

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Message-ID: <CA+V-a8sVdYm+P==2OzQ4QGFFREO4d_YtER_=9-g93Xsk8Nkz4w@mail.gmail.com>
Date: Mon, 18 Aug 2025 17:23:43 +0100
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Wolfram Sang <wsa+renesas@...g-engineering.com>
Cc: Clément Léger <clement.leger@...tlin.com>, 
	Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, 
	Russell King <linux@...linux.org.uk>, "David S. Miller" <davem@...emloft.net>, 
	Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, 
	Florian Fainelli <f.fainelli@...il.com>, Geert Uytterhoeven <geert+renesas@...der.be>, 
	linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, stable@...nel.org
Subject: Re: [PATCH] net: pcs-rzn1-miic: Correct MODCTRL register offset

Hi Wolfram,

Thank for the review.

On Mon, Aug 18, 2025 at 4:58 PM Wolfram Sang
<wsa+renesas@...g-engineering.com> wrote:
>
> On Mon, Aug 18, 2025 at 04:07:57PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Correct the Mode Control Register (MODCTRL) offset for RZ/N MIIC.
> > According to the R-IN Engine and Ethernet Peripherals Manual (Rev.1.30)
> > [0], Table 10.1 "Ethernet Accessory Register List", MODCTRL is at offset
> > 0x8, not 0x20 as previously defined.
> >
> > [0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054571
> >
> > Fixes: 7dc54d3b8d91 ("net: pcs: add Renesas MII converter driver")
> > Cc: stable@...nel.org
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Reviewed-by: Wolfram Sang <wsa+renesas@...g-engineering.com>
>
> I can also test it on my N1D board next week.
>
Perfect, I dont have access to the RZ/N1 board but I'm working on
reusing the same driver for a new SoC which has the same register.

Cheers,
Prabhakar