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Message-ID: <20250820171302.324142-2-ariel.dalessandro@collabora.com>
Date: Wed, 20 Aug 2025 14:12:49 -0300
From: Ariel D'Alessandro <ariel.dalessandro@...labora.com>
To: airlied@...il.com,
amergnat@...libre.com,
andrew+netdev@...n.ch,
andrew-ct.chen@...iatek.com,
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Cc: devicetree@...r.kernel.org,
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Subject: [PATCH v1 01/14] media: dt-bindings: Convert MediaTek mt8173-mdp bindings to YAML
Convert the existing text-based DT bindings for MediaTek MT8173 Media Data Path
to a YAML schema.
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@...labora.com>
---
.../bindings/media/mediatek,mt8173-mdp.yaml | 174 ++++++++++++++++++
.../bindings/media/mediatek-mdp.txt | 95 ----------
2 files changed, 174 insertions(+), 95 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
delete mode 100644 Documentation/devicetree/bindings/media/mediatek-mdp.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
new file mode 100644
index 0000000000000..f3a08afc305b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-mdp.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mt8173-mdp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT8173 Media Data Path
+
+maintainers:
+ - Ariel D'Alessandro <ariel.dalessandro@...labora.com>
+
+description:
+ Media Data Path is used for scaling and color space conversion.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - mediatek,mt8173-mdp-rdma
+ - mediatek,mt8173-mdp-rsz
+ - mediatek,mt8173-mdp-wdma
+ - mediatek,mt8173-mdp-wrot
+ - items:
+ - enum:
+ - mediatek,mt8173-mdp-rdma
+ - mediatek,mt8173-mdp-rsz
+ - mediatek,mt8173-mdp-wdma
+ - mediatek,mt8173-mdp-wrot
+ - const: mediatek,mt8173-mdp
+
+ reg:
+ maxItems: 1
+
+ clocks: true
+
+ power-domains:
+ maxItems: 1
+
+ iommus:
+ description: |
+ This property should point to the respective IOMMU block with master port as argument,
+ see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+ maxItems: 1
+
+ mediatek,vpu:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Describes point to vpu.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8173-mdp-rdma
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Main clock
+ - description: Mutex clock
+ else:
+ properties:
+ clocks:
+ items:
+ - description: Main clock
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8173-mdp-rdma
+ - mediatek,mt8173-mdp-wdma
+ - mediatek,mt8173-mdp-wrot
+ then:
+ required:
+ - iommus
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8173-mdp
+ then:
+ required:
+ - mediatek,vpu
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/memory/mt8173-larb-port.h>
+ #include <dt-bindings/power/mt8173-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mdp_rdma0: rdma@...01000 {
+ compatible = "mediatek,mt8173-mdp-rdma",
+ "mediatek,mt8173-mdp";
+ reg = <0 0x14001000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,vpu = <&vpu>;
+ };
+
+ mdp_rdma1: rdma@...02000 {
+ compatible = "mediatek,mt8173-mdp-rdma";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA1>,
+ <&mmsys CLK_MM_MUTEX_32K>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA1>;
+ };
+
+ mdp_rsz0: rsz@...03000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14003000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz1: rsz@...04000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14004000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_rsz2: rsz@...05000 {
+ compatible = "mediatek,mt8173-mdp-rsz";
+ reg = <0 0x14005000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ2>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ };
+
+ mdp_wdma0: wdma@...06000 {
+ compatible = "mediatek,mt8173-mdp-wdma";
+ reg = <0 0x14006000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA>;
+ };
+
+ mdp_wrot0: wrot@...07000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ };
+
+ mdp_wrot1: wrot@...08000 {
+ compatible = "mediatek,mt8173-mdp-wrot";
+ reg = <0 0x14008000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT1>;
+ power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
+ iommus = <&iommu M4U_PORT_MDP_WROT1>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt
deleted file mode 100644
index 53ef26e2c8570..0000000000000
--- a/Documentation/devicetree/bindings/media/mediatek-mdp.txt
+++ /dev/null
@@ -1,95 +0,0 @@
-* Mediatek Media Data Path
-
-Media Data Path is used for scaling and color space conversion.
-
-Required properties (controller node):
-- compatible: "mediatek,mt8173-mdp"
-- mediatek,vpu: the node of video processor unit, see
- Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
-
-Required properties (all function blocks, child node):
-- compatible: Should be one of
- "mediatek,mt8173-mdp-rdma" - read DMA
- "mediatek,mt8173-mdp-rsz" - resizer
- "mediatek,mt8173-mdp-wdma" - write DMA
- "mediatek,mt8173-mdp-wrot" - write DMA with rotation
-- reg: Physical base address and length of the function block register space
-- clocks: device clocks, see
- Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- power-domains: a phandle to the power domain, see
- Documentation/devicetree/bindings/power/power_domain.txt for details.
-
-Required properties (DMA function blocks, child node):
-- compatible: Should be one of
- "mediatek,mt8173-mdp-rdma"
- "mediatek,mt8173-mdp-wdma"
- "mediatek,mt8173-mdp-wrot"
-- iommus: should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
- for details.
-
-Example:
- mdp_rdma0: rdma@...01000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- "mediatek,mt8173-mdp";
- reg = <0 0x14001000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA0>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA0>;
- mediatek,vpu = <&vpu>;
- };
-
- mdp_rdma1: rdma@...02000 {
- compatible = "mediatek,mt8173-mdp-rdma";
- reg = <0 0x14002000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RDMA1>,
- <&mmsys CLK_MM_MUTEX_32K>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_RDMA1>;
- };
-
- mdp_rsz0: rsz@...03000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14003000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz1: rsz@...04000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14004000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_rsz2: rsz@...05000 {
- compatible = "mediatek,mt8173-mdp-rsz";
- reg = <0 0x14005000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_RSZ2>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- };
-
- mdp_wdma0: wdma@...06000 {
- compatible = "mediatek,mt8173-mdp-wdma";
- reg = <0 0x14006000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WDMA>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WDMA>;
- };
-
- mdp_wrot0: wrot@...07000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14007000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT0>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT0>;
- };
-
- mdp_wrot1: wrot@...08000 {
- compatible = "mediatek,mt8173-mdp-wrot";
- reg = <0 0x14008000 0 0x1000>;
- clocks = <&mmsys CLK_MM_MDP_WROT1>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- iommus = <&iommu M4U_PORT_MDP_WROT1>;
- };
--
2.50.1
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