netdev - RE: [Intel-wired-lan] [PATCH v9 iwl-next] ice: add recovery clock and clock 1588 control for E825c

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Message-ID: <IA1PR11MB6219ADDEA32B0C45C4CD0FED9203A@IA1PR11MB6219.namprd11.prod.outlook.com>
Date: Fri, 5 Sep 2025 14:54:00 +0000
From: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>
To: "Loktionov, Aleksandr" <aleksandr.loktionov@...el.com>,
	"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "pmenzel@...gen.mpg.de" <pmenzel@...gen.mpg.de>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, "Kubalewski, Arkadiusz"
	<arkadiusz.kubalewski@...el.com>, "Korba, Przemyslaw"
	<przemyslaw.korba@...el.com>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Olech, Milena" <milena.olech@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH v9 iwl-next] ice: add recovery clock and
 clock 1588 control for E825c

> -----Original Message-----
> From: Loktionov, Aleksandr <aleksandr.loktionov@...el.com>
> Sent: Wednesday, August 13, 2025 12:10 PM
> To: Nitka, Grzegorz <grzegorz.nitka@...el.com>; intel-wired-
> lan@...ts.osuosl.org
> Cc: pmenzel@...gen.mpg.de; netdev@...r.kernel.org; Kubalewski,
> Arkadiusz <arkadiusz.kubalewski@...el.com>; Korba, Przemyslaw
> <przemyslaw.korba@...el.com>; Nguyen, Anthony L
> <anthony.l.nguyen@...el.com>; Olech, Milena <milena.olech@...el.com>
> Subject: RE: [Intel-wired-lan] [PATCH v9 iwl-next] ice: add recovery clock and
> clock 1588 control for E825c
> 
> 
> 
> > -----Original Message-----
> > From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf
> > Of Grzegorz Nitka
> > Sent: Tuesday, August 12, 2025 10:20 PM
> > To: intel-wired-lan@...ts.osuosl.org
> > Cc: pmenzel@...gen.mpg.de; netdev@...r.kernel.org; Kubalewski,
> > Arkadiusz <arkadiusz.kubalewski@...el.com>; Korba, Przemyslaw
> > <przemyslaw.korba@...el.com>; Nguyen, Anthony L
> > <anthony.l.nguyen@...el.com>; Olech, Milena <milena.olech@...el.com>
> > Subject: [Intel-wired-lan] [PATCH v9 iwl-next] ice: add recovery
> > clock and clock 1588 control for E825c
> >
> > From: Przemyslaw Korba <przemyslaw.korba@...el.com>
> >
> > Add control for E825 input pins: phy clock recovery and clock 1588.
> > E825 does not provide control over platform level DPLL but it
> > provides control over PHY clock recovery, and PTP/timestamp driven
> > inputs for platform level DPLL [1].
> >
> > Introduce a software controlled layer of abstraction to:
> > - create a DPLL of type EEC for E825c,
> > - create recovered clock pin for each PF, and control them through
> > writing to registers,
> > - create pin to control clock 1588 for PF0, and control it through
> > writing to registers.
> >
> 
> ...
> 
> > +
> > +#define ICE_CGU_R10				0x28
> > +#define ICE_CGU_R10_SYNCE_CLKO_SEL		GENMASK(8, 5)
> > +#define ICE_CGU_R10_SYNCE_CLKODIV_M1
> 	GENMASK(13, 9)
> > +#define ICE_CGU_R10_SYNCE_CLKODIV_LOAD		BIT(14)
> > +#define ICE_CGU_R10_SYNCE_DCK_RST		BIT(15)
> > +#define ICE_CGU_R10_SYNCE_ETHCLKO_SEL
> 	GENMASK(18, 16)
> > +#define ICE_CGU_R10_SYNCE_ETHDIV_M1		GENMASK(23, 19)
> > +#define ICE_CGU_R10_SYNCE_ETHDIV_LOAD		BIT(24)
> > +#define ICE_CGU_R10_SYNCE_DCK2_RST		BIT(25)
> > +#define ICE_CGU_R10_SYNCE_S_REF_CLK		GENMASK(31, 27)
> > +
> > +#define ICE_CGU_R11				0x2C
> > +#define ICE_CGU_R11_SYNCE_S_BYP_CLK		GENMASK(6, 1)
> > +
> > +#define ICE_CGU_BYPASS_MUX_OFFSET_E825C		3
> > +
> > +#define SET_PIN_STATE(_pin, _id, _condition) \
> > +	((_pin)->state[_id] = (_condition) ? DPLL_PIN_STATE_CONNECTED
> > : \
> > +			       DPLL_PIN_STATE_DISCONNECTED)
> Can you consider implement it as inline function instead of macro?
> 
> Alex

Apologize for late response (summer break time). To be changed in v10.