netdev - RE: [PATCH v9 iwl-next] ice: add recovery clock and clock 1588 control for E825c

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Message-ID: <IA1PR11MB62196E5F77908DC155D3040E9203A@IA1PR11MB6219.namprd11.prod.outlook.com>
Date: Fri, 5 Sep 2025 15:00:48 +0000
From: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>
To: "intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Kubalewski, Arkadiusz"
	<arkadiusz.kubalewski@...el.com>, "pmenzel@...gen.mpg.de"
	<pmenzel@...gen.mpg.de>, "Korba, Przemyslaw" <przemyslaw.korba@...el.com>,
	"Olech, Milena" <milena.olech@...el.com>
Subject: RE: [PATCH v9 iwl-next] ice: add recovery clock and clock 1588
 control for E825c

> -----Original Message-----
> From: Nitka, Grzegorz <grzegorz.nitka@...el.com>
> Sent: Tuesday, August 12, 2025 10:20 PM
> To: intel-wired-lan@...ts.osuosl.org
> Cc: netdev@...r.kernel.org; Nguyen, Anthony L
> <anthony.l.nguyen@...el.com>; Kubalewski, Arkadiusz
> <arkadiusz.kubalewski@...el.com>; pmenzel@...gen.mpg.de; Korba,
> Przemyslaw <przemyslaw.korba@...el.com>; Olech, Milena
> <milena.olech@...el.com>; Nitka, Grzegorz <grzegorz.nitka@...el.com>
> Subject: [PATCH v9 iwl-next] ice: add recovery clock and clock 1588 control
> for E825c
> 
> From: Przemyslaw Korba <przemyslaw.korba@...el.com>
> 
> Add control for E825 input pins: phy clock recovery and clock 1588.
> E825 does not provide control over platform level DPLL but it
> provides control over PHY clock recovery, and PTP/timestamp driven
> inputs for platform level DPLL [1].
> 
> Introduce a software controlled layer of abstraction to:
> - create a DPLL of type EEC for E825c,
> - create recovered clock pin for each PF, and control them through
> writing to registers,
> - create pin to control clock 1588 for PF0, and control it through
> writing to registers.
> 
...
> @@ -3239,14 +3638,15 @@ static int ice_dpll_init_pins(struct ice_pf *pf, bool
> cgu)
>   * @d: pointer to ice_dpll
>   * @cgu: if cgu is present and controlled by this NIC
>   *
> - * If cgu is owned unregister the dpll from dpll subsystem.
> - * Release resources of dpll device from dpll subsystem.
> + * If cgu is owned or device is e825c, unregister the DPL from DPLL
> subsystem.
> + * Release resources of DPLL device from DPLL subsystem.
>   */
>  static void
>  ice_dpll_deinit_dpll(struct ice_pf *pf, struct ice_dpll *d, bool cgu)
>  {
> -	if (cgu)
> -		dpll_device_unregister(d->dpll, d->ops, d);
> +	if (cgu || (pf->hw.mac_type == ICE_MAC_GENERIC_3K_E825 &&
> +		    ice_pf_src_tmr_owned(pf)))
> +		dpll_device_unregister(d->dpll, &ice_dpll_ops, d);

d->ops should be passed as parameter to dpll_device_unregister() call.
This was mistakenly changed to ice_dpll_ops  while resolving conflicts
with "ice: add phase offset monitor for all PPS dpll inputs" commit.
To be fixed in v10.

>  	dpll_device_put(d->dpll);
>  }
>