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Message-ID: <0A3F1D1604FEE424+20250916012628.1819-1-kernel@airkyi.com>
Date: Tue, 16 Sep 2025 09:26:28 +0800
From: Chaoyi Chen <kernel@...kyi.com>
To: Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
"Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Jonas Karlman <jonas@...boo.se>,
David Wu <david.wu@...k-chips.com>
Cc: sebastian.reichel@...labora.com,
ziyao@...root.org,
netdev@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org,
Chaoyi Chen <chaoyi.chen@...k-chips.com>
Subject: [PATCH net-next] Revert "net: ethernet: stmmac: dwmac-rk: Make the clk_phy could be used for external phy"
From: Chaoyi Chen <chaoyi.chen@...k-chips.com>
This reverts commit da114122b83149d1f1db0586b1d67947b651aa20.
As discussed, the PHY clock should be managed by PHY driver instead
of other driver like dwmac-rk.
Signed-off-by: Chaoyi Chen <chaoyi.chen@...k-chips.com>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 266c53379236..49f92cd79aa8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -1410,15 +1410,12 @@ static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
clk_set_rate(plat->stmmac_clk, 50000000);
}
- if (plat->phy_node) {
+ if (plat->phy_node && bsp_priv->integrated_phy) {
bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
ret = PTR_ERR_OR_ZERO(bsp_priv->clk_phy);
- /* If it is not integrated_phy, clk_phy is optional */
- if (bsp_priv->integrated_phy) {
- if (ret)
- return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
- clk_set_rate(bsp_priv->clk_phy, 50000000);
- }
+ if (ret)
+ return dev_err_probe(dev, ret, "Cannot get PHY clock\n");
+ clk_set_rate(bsp_priv->clk_phy, 50000000);
}
return 0;
--
2.49.0
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