netdev - Re: [PATCH v19 06/22] cxl: Move pci generic code

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Message-ID: <20251007140113.000028ad@huawei.com>
Date: Tue, 7 Oct 2025 14:01:13 +0100
From: Jonathan Cameron <jonathan.cameron@...wei.com>
To: <alejandro.lucero-palau@....com>
CC: <linux-cxl@...r.kernel.org>, <netdev@...r.kernel.org>,
	<dan.j.williams@...el.com>, <edward.cree@....com>, <davem@...emloft.net>,
	<kuba@...nel.org>, <pabeni@...hat.com>, <edumazet@...gle.com>,
	<dave.jiang@...el.com>, Alejandro Lucero <alucerop@....com>, Ben Cheatham
	<benjamin.cheatham@....com>, Fan Ni <fan.ni@...sung.com>, Alison Schofield
	<alison.schofield@...el.com>
Subject: Re: [PATCH v19 06/22] cxl: Move pci generic code

On Mon, 6 Oct 2025 11:01:14 +0100
alejandro.lucero-palau@....com wrote:

> From: Alejandro Lucero <alucerop@....com>
> 
> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization
> meanwhile cxl/pci.c implements the functionality for a Type3 device
> initialization.
> 
> Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be
> exported and shared with CXL Type2 device initialization.
> 
> Fix cxl mock tests affected by the code move, deleting a function which
> indeed was not being used since commit 733b57f262b0("cxl/pci: Early
> setup RCH dport component registers from RCRB").
> 

Trivial but can we pull out that code removal as a separate patch?
It's something Dave would probably pick up immediately. 

> Signed-off-by: Alejandro Lucero <alucerop@....com>
> Reviewed-by: Dave Jiang <dave.jiang@...el.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@....com>
> Reviewed-by: Fan Ni <fan.ni@...sung.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
> Reviewed-by: Alison Schofield <alison.schofield@...el.com>
> Reviewed-by: Dan Williams <dan.j.williams@...el.com>


> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
> index ccf0ca36bc00..4b11757a46ab 100644
> --- a/drivers/cxl/cxlpci.h
> +++ b/drivers/cxl/cxlpci.h
> @@ -74,9 +74,22 @@ static inline bool cxl_pci_flit_256(struct pci_dev *pdev)
>  	return lnksta2 & PCI_EXP_LNKSTA2_FLIT;
>  }
>  
> +/*
> + * Assume that the caller has already validated that @pdev has CXL
> + * capabilities, any RCIEp with CXL capabilities is treated as a

In PCI spec they are RCiEP so we should match that rather than lowercase
for the P.

> + * Restricted CXL Device (RCD) and finds upstream port and endpoint
> + * registers in a Root Complex Register Block (RCRB).
> + */
> +static inline bool is_cxl_restricted(struct pci_dev *pdev)
> +{
> +	return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END;
> +}