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Message-ID: <20251007141822.00001c4a@huawei.com>
Date: Tue, 7 Oct 2025 14:18:22 +0100
From: Jonathan Cameron <jonathan.cameron@...wei.com>
To: <alejandro.lucero-palau@....com>
CC: <linux-cxl@...r.kernel.org>, <netdev@...r.kernel.org>,
<dan.j.williams@...el.com>, <edward.cree@....com>, <davem@...emloft.net>,
<kuba@...nel.org>, <pabeni@...hat.com>, <edumazet@...gle.com>,
<dave.jiang@...el.com>, Alejandro Lucero <alucerop@....com>, Ben Cheatham
<benjamin.cheatham@....com>
Subject: Re: [PATCH v19 07/22] cxl: allow Type2 drivers to map cxl component
regs
On Mon, 6 Oct 2025 11:01:15 +0100
alejandro.lucero-palau@....com wrote:
> From: Alejandro Lucero <alucerop@....com>
>
I'd amend the patch title to
cxl/sfc: Map CXL component regs.
And talk about exports in the description.
Other options are fine but the patch title should indicate
this is being used by the sfc driver.
> Export cxl core functions for a Type2 driver being able to discover and
> map the device component registers.
>
> Use it in sfc driver cxl initialization.
>
> Signed-off-by: Alejandro Lucero <alucerop@....com>
> Reviewed-by: Dan Williams <dan.j.williams@...el.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
> Reviewed-by: Dave Jiang <dave.jiang@...el.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@....com>
> ---
> drivers/cxl/core/pci.c | 1 +
> drivers/cxl/core/port.c | 1 +
> drivers/cxl/core/regs.c | 1 +
> drivers/cxl/cxl.h | 7 ------
> drivers/cxl/cxlpci.h | 12 ----------
> drivers/cxl/pci.c | 1 +
> drivers/net/ethernet/sfc/efx_cxl.c | 35 ++++++++++++++++++++++++++++++
> include/cxl/cxl.h | 19 ++++++++++++++++
> include/cxl/pci.h | 21 ++++++++++++++++++
> 9 files changed, 79 insertions(+), 19 deletions(-)
> create mode 100644 include/cxl/pci.h
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