netdev - Re: [PATCH v5 net-next 02/14] gro: flushing when CWR is set negatively affects AccECN

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Message-ID: <8ac38ae2-74fc-45a1-88fb-4edd124ab9c3@redhat.com>
Date: Thu, 6 Nov 2025 12:08:08 +0100
From: Paolo Abeni <pabeni@...hat.com>
To: chia-yu.chang@...ia-bell-labs.com, edumazet@...gle.com, parav@...dia.com,
 linux-doc@...r.kernel.org, corbet@....net, horms@...nel.org,
 dsahern@...nel.org, kuniyu@...gle.com, bpf@...r.kernel.org,
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Subject: Re: [PATCH v5 net-next 02/14] gro: flushing when CWR is set
 negatively affects AccECN

On 11/6/25 12:01 PM, Paolo Abeni wrote:
> On 10/30/25 3:34 PM, chia-yu.chang@...ia-bell-labs.com wrote:
>> From: Ilpo Järvinen <ij@...nel.org>
>>
>> As AccECN may keep CWR bit asserted due to different
>> interpretation of the bit, flushing with GRO because of
>> CWR may effectively disable GRO until AccECN counter
>> field changes such that CWR-bit becomes 0.
>>
>> There is no harm done from not immediately forwarding the
>> CWR'ed segment with RFC3168 ECN.
>>
>> Signed-off-by: Ilpo Järvinen <ij@...nel.org>
>> Signed-off-by: Chia-Yu Chang <chia-yu.chang@...ia-bell-labs.com>
> 
> Please provide a test/update the existing one to cover this case or move
> to a later series. Possibly both :)

Whoops, sorry. I'm looking at the patch in order and when I wrote the
above I haven't seen yet patch 4/14. Please ignore.

/P