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Message-ID: <0383a8e8-1713-438e-86c6-69c8b01cfb48@bootlin.com>
Date: Wed, 12 Nov 2025 16:50:51 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
"David S. Miller" <davem@...emloft.net>,
Emil Renner Berthing <kernel@...il.dk>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Keguang Zhang <keguang.zhang@...il.com>,
linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
linux-mips@...r.kernel.org, linux-stm32@...md-mailman.stormreply.com,
Matthias Brugger <matthias.bgg@...il.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Minda Chen <minda.chen@...rfivetech.com>, netdev@...r.kernel.org,
Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@...l.toshiba>,
Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next v2 05/13] net: stmmac: mediatek: use
stmmac_get_phy_intf_sel()
On 11/11/2025 09:12, Russell King (Oracle) wrote:
> Use stmmac_get_phy_intf_sel() to decode the PHY interface mode to the
> phy_intf_sel value, validate the result, and pass that into the
> implementation specific ->dwmac_set_phy_interface() method. Use this
> to configure the PHY interface selection field.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
Reviewed-by: Maxime Chevallier <maxime.chevallier@...tlin.com>
Maxime
> ---
> .../ethernet/stmicro/stmmac/dwmac-mediatek.c | 43 +++++++++++--------
> 1 file changed, 25 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> index dcdf28418fec..0f32732efb75 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
> @@ -85,7 +85,8 @@ struct mediatek_dwmac_plat_data {
> };
>
> struct mediatek_dwmac_variant {
> - int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
> + int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat,
> + u8 phy_intf_sel);
> int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
>
> /* clock ids to be requested */
> @@ -106,25 +107,25 @@ static const char * const mt8195_dwmac_clk_l[] = {
> "axi", "apb", "mac_cg", "mac_main", "ptp_ref"
> };
>
> -static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
> +static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat,
> + u8 phy_intf_sel)
> {
> int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
> int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
> - u32 intf_val = 0;
> + u32 intf_val;
> +
> + intf_val = phy_intf_sel;
>
> /* select phy interface in top control domain */
> switch (plat->phy_mode) {
> - case PHY_INTERFACE_MODE_MII:
> - intf_val |= PHY_INTF_SEL_GMII_MII;
> - break;
> case PHY_INTERFACE_MODE_RMII:
> - intf_val |= PHY_INTF_SEL_RMII | rmii_rxc | rmii_clk_from_mac;
> + intf_val |= rmii_rxc | rmii_clk_from_mac;
> break;
> + case PHY_INTERFACE_MODE_MII:
> case PHY_INTERFACE_MODE_RGMII:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> case PHY_INTERFACE_MODE_RGMII_RXID:
> case PHY_INTERFACE_MODE_RGMII_ID:
> - intf_val |= PHY_INTF_SEL_RGMII;
> break;
> default:
> dev_err(plat->dev, "phy interface not supported\n");
> @@ -285,27 +286,25 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
> .tx_delay_max = 17600,
> };
>
> -static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
> +static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
> + u8 phy_intf_sel)
> {
> int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
> int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
> - u32 intf_val = 0;
> + u32 intf_val;
> +
> + intf_val = FIELD_PREP(MT8195_ETH_INTF_SEL, phy_intf_sel);
>
> /* select phy interface in top control domain */
> switch (plat->phy_mode) {
> - case PHY_INTERFACE_MODE_MII:
> - intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL,
> - PHY_INTF_SEL_GMII_MII);
> - break;
> case PHY_INTERFACE_MODE_RMII:
> intf_val |= rmii_rxc | rmii_clk_from_mac;
> - intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_SEL_RMII);
> break;
> + case PHY_INTERFACE_MODE_MII:
> case PHY_INTERFACE_MODE_RGMII:
> case PHY_INTERFACE_MODE_RGMII_TXID:
> case PHY_INTERFACE_MODE_RGMII_RXID:
> case PHY_INTERFACE_MODE_RGMII_ID:
> - intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_SEL_RGMII);
> break;
> default:
> dev_err(plat->dev, "phy interface not supported\n");
> @@ -525,10 +524,18 @@ static int mediatek_dwmac_init(struct device *dev, void *priv)
> {
> struct mediatek_dwmac_plat_data *plat = priv;
> const struct mediatek_dwmac_variant *variant = plat->variant;
> - int ret;
> + int phy_intf_sel, ret;
>
> if (variant->dwmac_set_phy_interface) {
> - ret = variant->dwmac_set_phy_interface(plat);
> + phy_intf_sel = stmmac_get_phy_intf_sel(plat->phy_mode);
> + if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
> + phy_intf_sel != PHY_INTF_SEL_RGMII &&
> + phy_intf_sel != PHY_INTF_SEL_RMII) {
> + dev_err(plat->dev, "phy interface not supported\n");
> + return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
> + }
> +
> + ret = variant->dwmac_set_phy_interface(plat, phy_intf_sel);
> if (ret) {
> dev_err(dev, "failed to set phy interface, err = %d\n", ret);
> return ret;
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