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Message-ID: <dfa8b826-4f8b-4389-827f-82102239531d@intel.com>
Date: Mon, 1 Dec 2025 14:05:35 +0200
From: "Lifshits, Vitaly" <vitaly.lifshits@...el.com>
To: Andrew Lunn <andrew@...n.ch>
CC: <intel-wired-lan@...osl.org>, <netdev@...r.kernel.org>,
	<andrew+netdev@...n.ch>, <horms@...nel.org>, <kuba@...nel.org>,
	<edumazet@...gle.com>, <davem@...emloft.net>, <pabeni@...hat.com>
Subject: Re: [PATCH iwl-next v1 1/1] e1000e: introduce private flag to
 override XTAL clock frequency



On 11/27/2025 9:16 PM, Andrew Lunn wrote:
> On Thu, Nov 27, 2025 at 06:30:47AM +0200, Vitaly Lifshits wrote:
>> On some TGP and ADP systems, the hardware XTAL clock is incorrectly
>> set to 24MHz instead of the expected 38.4MHz, causing PTP timer
>> inaccuracies. Since affected systems cannot be reliably detected,
>> introduce an ethtool private flag that allows user-space to override
>> the XTAL clock frequency.
> 
> Why cannot it be reliably detected? The timer is running at 62% the
> expected speed. Cannot you read it twice with a 1ms sleep in the
> middle and see the difference?
> 

Thanks for the suggestion. The approach might not be very elegant, but 
I'll check if it works. If it does, I agree it would be better than 
making the frequency configurable.

>>   #define FLAG2_DFLT_CRC_STRIPPING          BIT(12)
>>   #define FLAG2_CHECK_RX_HWTSTAMP           BIT(13)
>>   #define FLAG2_CHECK_SYSTIM_OVERFLOW       BIT(14)
>> -#define FLAG2_ENABLE_S0IX_FLOWS           BIT(15)
>> -#define FLAG2_DISABLE_K1		   BIT(16)
>> +
>> +#define PRIV_FLAG_ENABLE_S0IX_FLOWS	   BIT(0)
>> +#define PRIV_FLAG_DISABLE_K1		   BIT(1)
>> +#define PRIV_FLAG_38_4MHZ_XTAL_CLK	   BIT(2)
> 
> Please split this up. Rename of FLAG2_ENABLE_S0IX_FLOWS and
> FLAG2_DISABLE_K1 in one patch, 24MHz in another patch. That will make
> review easier.
> 
>         Andrew

If the detection method proves unreliable, I'll split this patch into 
two commits as you suggested: one for renaming the flags and another for 
adding the XTAL clock override.

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