netdev - Re: [PATCH iwl-next v1 1/1] e1000e: introduce private flag to override XTAL clock frequency

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Message-ID: <a60a2c81-658a-4bfc-a0dd-59941676bf00@lunn.ch>
Date: Thu, 27 Nov 2025 20:16:10 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Vitaly Lifshits <vitaly.lifshits@...el.com>
Cc: intel-wired-lan@...osl.org, netdev@...r.kernel.org,
	andrew+netdev@...n.ch, horms@...nel.org, kuba@...nel.org,
	edumazet@...gle.com, davem@...emloft.net, pabeni@...hat.com
Subject: Re: [PATCH iwl-next v1 1/1] e1000e: introduce private flag to
 override XTAL clock frequency

On Thu, Nov 27, 2025 at 06:30:47AM +0200, Vitaly Lifshits wrote:
> On some TGP and ADP systems, the hardware XTAL clock is incorrectly
> set to 24MHz instead of the expected 38.4MHz, causing PTP timer
> inaccuracies. Since affected systems cannot be reliably detected,
> introduce an ethtool private flag that allows user-space to override
> the XTAL clock frequency.

Why cannot it be reliably detected? The timer is running at 62% the
expected speed. Cannot you read it twice with a 1ms sleep in the
middle and see the difference?

>  #define FLAG2_DFLT_CRC_STRIPPING          BIT(12)
>  #define FLAG2_CHECK_RX_HWTSTAMP           BIT(13)
>  #define FLAG2_CHECK_SYSTIM_OVERFLOW       BIT(14)
> -#define FLAG2_ENABLE_S0IX_FLOWS           BIT(15)
> -#define FLAG2_DISABLE_K1		   BIT(16)
> +
> +#define PRIV_FLAG_ENABLE_S0IX_FLOWS	   BIT(0)
> +#define PRIV_FLAG_DISABLE_K1		   BIT(1)
> +#define PRIV_FLAG_38_4MHZ_XTAL_CLK	   BIT(2)

Please split this up. Rename of FLAG2_ENABLE_S0IX_FLOWS and
FLAG2_DISABLE_K1 in one patch, 24MHz in another patch. That will make
review easier.

       Andrew