netdev - Re: [net-next,PATCH 3/3] net: phy: realtek: Add property to enable SSC

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Message-ID: <75fb955d-ef53-4e59-8a9c-d9792f6e6466@mailbox.org>
Date: Wed, 3 Dec 2025 21:56:40 +0100
From: Marek Vasut <marek.vasut@...lbox.org>
To: Ivan Galkin <Ivan.Galkin@...s.com>,
 "vladimir.oltean@....com" <vladimir.oltean@....com>
Cc: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
 "andrew@...n.ch" <andrew@...n.ch>, "davem@...emloft.net"
 <davem@...emloft.net>, "hkallweit1@...il.com" <hkallweit1@...il.com>,
 "michael@...sekall.de" <michael@...sekall.de>,
 "pabeni@...hat.com" <pabeni@...hat.com>, "robh@...nel.org"
 <robh@...nel.org>, "linux@...linux.org.uk" <linux@...linux.org.uk>,
 "olek2@...pl" <olek2@...pl>, "f.fainelli@...il.com" <f.fainelli@...il.com>,
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 <kuba@...nel.org>
Subject: Re: [net-next,PATCH 3/3] net: phy: realtek: Add property to enable
 SSC

On 12/3/25 3:18 PM, Ivan Galkin wrote:

> - Regarding RTL8211F(D)(I)-VD-CG
> 
> As I mentioned before, saying that PHYCR2 doesn't exist is incorrect.
> However, the SSC settings have indeed been moved away from PHYCR2 as
> well.
> 
> The procedure for enabling of RXC SSC and CLKOUT SSC is described in
> EMI Improvement Application Note v1.0 for RTL8211F(D)(I)-VD-CG.

I have EMI improvement application note v1.2 for RTL8211F(D)(I)-CG .

> Enable RXC SSC: Page 0x0d15, register 0x16, Bit 13.
> '1' enables default Main Tone Degrade option (aka "middle").

Page 0xc44 register 0x13 = 0x5f00

> Enable CLK_OUT SSC: This depends on the CLKOUT frequency and the Main
> Tone Degrade option.
> The sequence is complicated and involves several pages and registers.
> The application suggests setting those registers to predefined 16-bit
> values, which I struggle to interpret.
> I would redirect you to the application note instead. All I can say is
> that PHYCR2 (page 0xa43, address 0x19) is not involved.

Page 0xd09 register 0x10 = 0xcf00
Page 0xa43 register 0x19 = 0x38c3
... and, I also suspect this needs to be done, but is missing in the 
appnote ...
PHYCR2 |= BIT(7) // and maybe also bits 13:12 ?

> - Regarding other RTL8211F PHYs.
> I compared datasheets for RTL8211F(I)/RTL8211FD(I) and RTL8211FS(I)(-
> VS). They both use the following bits:
> 
> PHYCR2 (page 0xa43, address 0x19)
> bit 3: enables SSC on RXC clock output
> bit 7: enables SSC on CLKOUT output clock
> 
> Both SSCs are controlled over PHYCR2, which, as far as I can see,
> contradicts this patch.

The bit 7 part is missing from the EMI appnote for RTL8211F(D)(I)-CG , I 
will add it in V2.

-- 
Best regards,
Marek Vasut