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Message-ID: <20260107134503.3437226-1-vimleshk@marvell.com>
Date: Wed, 7 Jan 2026 13:45:02 +0000
From: Vimlesh Kumar <vimleshk@...vell.com>
To: <netdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: <sedara@...vell.com>, <srasheed@...vell.com>, <hgani@...vell.com>,
"Vimlesh Kumar" <vimleshk@...vell.com>,
Veerasenareddy Burru
<vburru@...vell.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller"
<davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski
<kuba@...nel.org>,
"Paolo Abeni" <pabeni@...hat.com>
Subject: [PATCH net-next v3] octeon_ep: reset firmware ready status
Add support to reset firmware ready status
when the driver is removed(either in unload
or unbind)
Signed-off-by: Sathesh Edara <sedara@...vell.com>
Signed-off-by: Shinas Rasheed <srasheed@...vell.com>
Signed-off-by: Vimlesh Kumar <vimleshk@...vell.com>
---
V3:
- Reformat code to less than 80 columns wide.
- Use #defines for register constants.
V2: Use recommended bit manipulation macros.
V1: https://lore.kernel.org/all/20251120112345.649021-2-vimleshk@marvell.com/
.../marvell/octeon_ep/octep_cn9k_pf.c | 26 +++++++++++++++++++
.../marvell/octeon_ep/octep_cnxk_pf.c | 2 +-
.../marvell/octeon_ep/octep_regs_cn9k_pf.h | 23 ++++++++++++++++
.../marvell/octeon_ep/octep_regs_cnxk_pf.h | 1 +
4 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
index b5805969404f..686a3259ccb8 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
@@ -637,6 +637,19 @@ static int octep_soft_reset_cn93_pf(struct octep_device *oct)
octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF);
+ /* Firmware status CSR is supposed to be cleared by
+ * core domain reset, but due to a hw bug, it is not.
+ * Set it to RUNNING right before reset so that it is not
+ * left in READY (1) state after a reset. This is required
+ * in addition to the early setting to handle the case where
+ * the OcteonTX is unexpectedly reset, reboots, and then
+ * the module is removed.
+ */
+ OCTEP_PCI_WIN_WRITE(oct,
+ CN9K_PEMX_PFX_CSX_PFCFGX(0,
+ 0, CN9K_PCIEEP_VSECST_CTL),
+ FW_STATUS_DOWNING);
+
/* Set core domain reset bit */
OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1);
/* Wait for 100ms as Octeon resets. */
@@ -894,4 +907,17 @@ void octep_device_setup_cn93_pf(struct octep_device *oct)
octep_init_config_cn93_pf(oct);
octep_configure_ring_mapping_cn93_pf(oct);
+
+ if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF)
+ return;
+
+ /* Firmware status CSR is supposed to be cleared by
+ * core domain reset, but due to IPBUPEM-38842, it is not.
+ * Set it to RUNNING early in boot, so that unexpected resets
+ * leave it in a state that is not READY (1).
+ */
+ OCTEP_PCI_WIN_WRITE(oct,
+ CN9K_PEMX_PFX_CSX_PFCFGX(0,
+ 0, CN9K_PCIEEP_VSECST_CTL),
+ FW_STATUS_RUNNING);
}
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
index 5de0b5ecbc5f..e07264b3dbf8 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
@@ -660,7 +660,7 @@ static int octep_soft_reset_cnxk_pf(struct octep_device *oct)
* the module is removed.
*/
OCTEP_PCI_WIN_WRITE(oct, CNXK_PEMX_PFX_CSX_PFCFGX(0, 0, CNXK_PCIEEP_VSECST_CTL),
- FW_STATUS_RUNNING);
+ FW_STATUS_DOWNING);
/* Set chip domain reset bit */
OCTEP_PCI_WIN_WRITE(oct, CNXK_RST_CHIP_DOMAIN_W1S, 1);
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
index ca473502d7a0..8ad6f229ffeb 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h
@@ -5,6 +5,8 @@
*
*/
+#include <linux/bitfield.h>
+
#ifndef _OCTEP_REGS_CN9K_PF_H_
#define _OCTEP_REGS_CN9K_PF_H_
@@ -383,6 +385,27 @@
/* bit 1 for firmware heartbeat interrupt */
#define CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1)
+#define FW_STATUS_DOWNING 0ULL
+#define FW_STATUS_RUNNING 2ULL
+
+#define CN9K_PEM_GENMASK BIT_ULL(36)
+#define CN9K_PF_GENMASK GENMASK_ULL(21, 18)
+#define CN9K_PFX_CSX_PFCFGX_SHADOW_BIT BIT_ULL(16)
+#define CN9K_PFX_CSX_PFCFGX_BASE_ADDR (0x8e0000008000ULL)
+#define CN9K_4BYTE_ALIGNED_ADDRESS_OFFSET(offset) ((offset) & BIT_ULL(2))
+#define CN9K_PEMX_PFX_CSX_PFCFGX(pem, pf, offset)\
+ ({ typeof(offset) _off = (offset);\
+ ((CN9K_PFX_CSX_PFCFGX_BASE_ADDR\
+ | (uint64_t)FIELD_PREP(CN9K_PEM_GENMASK, pem)\
+ | FIELD_PREP(CN9K_PF_GENMASK, pf)\
+ | (CN9K_PFX_CSX_PFCFGX_SHADOW_BIT & (_off))\
+ | (rounddown((_off), 8)))\
+ + (CN9K_4BYTE_ALIGNED_ADDRESS_OFFSET(_off)));\
+ })
+
+/* Register defines for use with CN9K_PEMX_PFX_CSX_PFCFGX */
+#define CN9K_PCIEEP_VSECST_CTL 0x4D0
+
#define CN93_PEM_BAR4_INDEX 7
#define CN93_PEM_BAR4_INDEX_SIZE 0x400000ULL
#define CN93_PEM_BAR4_INDEX_OFFSET (CN93_PEM_BAR4_INDEX * CN93_PEM_BAR4_INDEX_SIZE)
diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
index e637d7c8224d..a6b6c9f356de 100644
--- a/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
+++ b/drivers/net/ethernet/marvell/octeon_ep/octep_regs_cnxk_pf.h
@@ -396,6 +396,7 @@
#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX BIT_ULL(0)
/* bit 1 for firmware heartbeat interrupt */
#define CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT BIT_ULL(1)
+#define FW_STATUS_DOWNING 0ULL
#define FW_STATUS_RUNNING 2ULL
#define CNXK_PEMX_PFX_CSX_PFCFGX(pem, pf, offset) ({ typeof(offset) _off = (offset); \
((0x8e0000008000 | \
--
2.47.0
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