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Message-ID: <20260113021845.411-1-javen_xu@realsil.com.cn>
Date: Tue, 13 Jan 2026 10:18:44 +0800
From: javen <javen_xu@...lsil.com.cn>
To: <hkallweit1@...il.com>
CC: <andrew+netdev@...n.ch>, <davem@...emloft.net>, <edumazet@...gle.com>,
        <horms@...nel.org>, <javen_xu@...lsil.com.cn>, <kuba@...nel.org>,
        <linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
        <nic_swsd@...ltek.com>, <pabeni@...hat.com>
Subject: Re: [PATCH net-next v1 3/3] r8169: add support for chip RTL9151AS

> On 1/12/2026 3:45 AM, javen wrote:
> > From: Javen Xu <javen_xu@...lsil.com.cn>
> >
> > This patch adds support for chip RTL9151AS. Since lacking of Hardware
> > version IDs, we use TX_CONFIG_V2 to recognize RTL9151AS and coming
> chips.
> > rtl_chip_infos_extend is used to store IC information for RTL9151AS
> > and coming chips. The TxConfig value between RTL9151AS and RTL9151A is
> >
> > different.
> >
> > Signed-off-by: Javen Xu <javen_xu@...lsil.com.cn>
> > ---
> >  drivers/net/ethernet/realtek/r8169.h      |  3 ++-
> >  drivers/net/ethernet/realtek/r8169_main.c | 28
> > +++++++++++++++++++++--
> >  2 files changed, 28 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/realtek/r8169.h
> > b/drivers/net/ethernet/realtek/r8169.h
> > index 2c1a0c21af8d..f66c279cbee6 100644
> > --- a/drivers/net/ethernet/realtek/r8169.h
> > +++ b/drivers/net/ethernet/realtek/r8169.h
> > @@ -72,7 +72,8 @@ enum mac_version {
> >       RTL_GIGA_MAC_VER_70,
> >       RTL_GIGA_MAC_VER_80,
> >       RTL_GIGA_MAC_NONE,
> > -     RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1
> > +     RTL_GIGA_MAC_VER_LAST = RTL_GIGA_MAC_NONE - 1,
> > +     RTL_GIGA_MAC_VER_CHECK_EXTEND
> >  };
> >
> >  struct rtl8169_private;
> > diff --git a/drivers/net/ethernet/realtek/r8169_main.c
> > b/drivers/net/ethernet/realtek/r8169_main.c
> > index 9b89bbf67198..164ad6570059 100644
> > --- a/drivers/net/ethernet/realtek/r8169_main.c
> > +++ b/drivers/net/ethernet/realtek/r8169_main.c
> > @@ -95,8 +95,8 @@
> >  #define JUMBO_16K    (SZ_16K - VLAN_ETH_HLEN - ETH_FCS_LEN)
> >
> >  static const struct rtl_chip_info {
> > -     u16 mask;
> > -     u16 val;
> > +     u32 mask;
> > +     u32 val;
> >       enum mac_version mac_version;
> >       const char *name;
> >       const char *fw_name;
> > @@ -205,10 +205,20 @@ static const struct rtl_chip_info {
> >       { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03, "RTL8110s" },
> >       { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02, "RTL8169s" },
> >
> > +     /* extend chip version*/
> > +     { 0x7cf, 0x7c8, RTL_GIGA_MAC_VER_CHECK_EXTEND },
> > +
> >       /* Catch-all */
> >       { 0x000, 0x000, RTL_GIGA_MAC_NONE }  };
> >
> > +static const struct rtl_chip_info rtl_chip_infos_extend[] = {
> > +     { 0x7fffffff, 0x00000000, RTL_GIGA_MAC_VER_64, "RTL9151AS",
> > +FIRMWARE_9151A_1},
> > +
> 
> Seems all bits except bit 31 are used for chip detection. However register is
> named TX_CONFIG_V2, even though only bit 31 is left for actual tx
> configuration.
> Is the register name misleading, or is the mask incorrect?
> 

Previously, we used TxConfig for chip detection. But considering that the 
remaining version IDs are limited, we need to extend it. To remain the 
consistency of name, we choose TX_CONFIG_V2 to extend it. Bit 31 is 
reserved and always 0. Only if nic link drop, it will be set to 1.
 
> > +     /* Catch-all */
> > +     { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } };
> > +
> >  static const struct pci_device_id rtl8169_pci_tbl[] = {
> >       { PCI_VDEVICE(REALTEK,  0x2502) },
> >       { PCI_VDEVICE(REALTEK,  0x2600) }, @@ -255,6 +265,8 @@ enum
> > rtl_registers {
> >       IntrStatus      = 0x3e,
> >
> >       TxConfig        = 0x40,
> > +     /* Extend version register */
> > +     TX_CONFIG_V2    = 0x60b0,
> >  #define      TXCFG_AUTO_FIFO                 (1 << 7)        /* 8111e-vl */
> >  #define      TXCFG_EMPTY                     (1 << 11)       /* 8111e-vl */
> >
> > @@ -2351,6 +2363,15 @@ static const struct ethtool_ops
> rtl8169_ethtool_ops = {
> >       .get_eth_ctrl_stats     = rtl8169_get_eth_ctrl_stats,
> >  };
> >
> > +static const struct rtl_chip_info
> > +*rtl8169_get_extend_chip_version(u32 txconfigv2) {
> > +     const struct rtl_chip_info *p = rtl_chip_infos_extend;
> > +
> > +     while ((txconfigv2 & p->mask) != p->val)
> > +             p++;
> > +     return p;
> > +}
> > +
> >  static const struct rtl_chip_info *rtl8169_get_chip_version(u16 xid,
> > bool gmii)  {
> >       /* Chips combining a 1Gbps MAC with a 100Mbps PHY */ @@ -5543,6
> > +5564,9 @@ static int rtl_init_one(struct pci_dev *pdev, const struct
> > pci_device_id *ent)
> >
> >       /* Identify chip attached to board */
> >       chip = rtl8169_get_chip_version(xid, tp->supports_gmii);
> > +
> > +     if (chip->mac_version == RTL_GIGA_MAC_VER_CHECK_EXTEND)
> > +             chip = rtl8169_get_extend_chip_version(RTL_R32(tp,
> > + TX_CONFIG_V2));
> >       if (chip->mac_version == RTL_GIGA_MAC_NONE)
> >               return dev_err_probe(&pdev->dev, -ENODEV,
> >                                    "unknown chip XID %03x, contact
> > r8169 maintainers (see MAINTAINERS file)\n",

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