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Message-ID: <CA+HBbNFYBhtvUxd45O7eP_1JYENxeGZOkA+yUsEdztOSSi9Gdg@mail.gmail.com>
Date: Tue, 13 Jan 2026 21:09:40 +0100
From: Robert Marko <robert.marko@...tura.hr>
To: claudiu beznea <claudiu.beznea@...on.dev>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
nicolas.ferre@...rochip.com, alexandre.belloni@...tlin.com,
herbert@...dor.apana.org.au, davem@...emloft.net, vkoul@...nel.org,
andi.shyti@...nel.org, lee@...nel.org, andrew+netdev@...n.ch,
edumazet@...gle.com, kuba@...nel.org, pabeni@...hat.com, linusw@...nel.org,
Steen.Hegelund@...rochip.com, daniel.machon@...rochip.com,
UNGLinuxDriver@...rochip.com, olivia@...enic.com, radu_nicolae.pirea@....ro,
richard.genoud@...tlin.com, gregkh@...uxfoundation.org, jirislaby@...nel.org,
broonie@...nel.org, lars.povlsen@...rochip.com, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-crypto@...r.kernel.org, dmaengine@...r.kernel.org,
linux-i2c@...r.kernel.org, netdev@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-spi@...r.kernel.org, linux-serial@...r.kernel.org,
linux-usb@...r.kernel.org, luka.perkov@...tura.hr
Subject: Re: [PATCH v4 15/15] arm64: dts: microchip: add EV23X71A board
On Sun, Jan 11, 2026 at 3:42 PM claudiu beznea <claudiu.beznea@...on.dev> wrote:
>
> Hi, Robert,
>
> On 12/29/25 20:37, Robert Marko wrote:
> > Microchip EV23X71A is an LAN9696 based evaluation board.
> >
> > Signed-off-by: Robert Marko <robert.marko@...tura.hr>
> > ---
> > Changes in v2:
> > * Split from SoC DTSI commit
> > * Apply DTS coding style
> > * Enclose array in i2c-mux
> > * Alphanumericaly sort nodes
> > * Change management port mode to RGMII-ID
> >
> > arch/arm64/boot/dts/microchip/Makefile | 1 +
> > .../boot/dts/microchip/lan9696-ev23x71a.dts | 757 ++++++++++++++++++
> > 2 files changed, 758 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts
> >
> > diff --git a/arch/arm64/boot/dts/microchip/Makefile b/arch/arm64/boot/dts/microchip/Makefile
> > index c6e0313eea0f..09d16fc1ce9a 100644
> > --- a/arch/arm64/boot/dts/microchip/Makefile
> > +++ b/arch/arm64/boot/dts/microchip/Makefile
> > @@ -1,4 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0
> > +dtb-$(CONFIG_ARCH_LAN969X) += lan9696-ev23x71a.dtb
> > dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
> > dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb
> > dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
> > diff --git a/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts
> > new file mode 100644
> > index 000000000000..435df455b078
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/microchip/lan9696-ev23x71a.dts
>
> [ ...]
>
> > +&gpio {
> > + emmc_sd_pins: emmc-sd-pins {
> > + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */
> > + pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17",
> > + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21",
> > + "GPIO_22", "GPIO_23", "GPIO_24";
> > + function = "emmc_sd";
> > + };
> > +
> > + fan_pins: fan-pins {
> > + pins = "GPIO_25", "GPIO_26";
> > + function = "fan";
> > + };
> > +
> > + fc0_pins: fc0-pins {
> > + pins = "GPIO_3", "GPIO_4";
> > + function = "fc";
> > + };
> > +
> > + fc2_pins: fc2-pins {
> > + pins = "GPIO_64", "GPIO_65", "GPIO_66";
> > + function = "fc";
> > + };
> > +
> > + fc3_pins: fc3-pins {
> > + pins = "GPIO_55", "GPIO_56";
> > + function = "fc";
> > + };
> > +
> > + mdio_pins: mdio-pins {
> > + pins = "GPIO_9", "GPIO_10";
> > + function = "miim";
> > + };
> > +
> > + mdio_irq_pins: mdio-irq-pins {
> > + pins = "GPIO_11";
> > + function = "miim_irq";
> > + };
> > +
> > + sgpio_pins: sgpio-pins {
> > + /* SCK, D0, D1, LD */
> > + pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8";
> > + function = "sgpio_a";
> > + };
> > +
> > + usb_ulpi_pins: usb-ulpi-pins {
> > + pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33",
> > + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37",
> > + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41";
> > + function = "usb_ulpi";
> > + };
> > +
> > + usb_rst_pins: usb-rst-pins {
> > + pins = "GPIO_12";
> > + function = "usb2phy_rst";
> > + };
> > +
> > + usb_over_pins: usb-over-pins {
> > + pins = "GPIO_13";
> > + function = "usb_over_detect";
> > + };
> > +
> > + usb_power_pins: usb-power-pins {
> > + pins = "GPIO_1";
> > + function = "usb_power";
> > + };
> > +
> > + ptp_out_pins: ptp-out-pins {
> > + pins = "GPIO_58";
> > + function = "ptpsync_4";
> > + };
>
> Could you please move this one upper to have all the entries in the gpio
> container alphanumerically sorted?
>
> > +
> > + ptp_ext_pins: ptp-ext-pins {
> > + pins = "GPIO_59";
> > + function = "ptpsync_5";
> > + };
>
> Same here.
Sure, I will make sure that pin nodes are alphabetical (I found some
more that are not) in v5.
>
> [ ...]
>
> > + port29: port@29 {
> > + reg = <29>;
> > + phys = <&serdes 11>;
> > + phy-handle = <&phy3>;
> > + phy-mode = "rgmii-id";
> > + microchip,bandwidth = <1000>;
>
> There are some questions around this node from Andrew in v1 of this series,
> which I don't see an answer for in any of the following versions. Could you
> please clarify?
Sure, as for the RGMII I switched to rgmii-id so the PHY is adding the delays.
Though, I am not sure if its better to add them via MAC as it can add
the delays instead of the PHY,
so I am open to suggestions here.
As for the phys property, yes that is not required here as RGMII ports
are dedicated, there are no
SERDES lanes being used for them.
I have updated the bindings to account for this and it will be part of v5.
Regards,
Robert
>
> The rest looks good to me.
>
> Thank you,
> Claudiu
>
--
Robert Marko
Staff Embedded Linux Engineer
Sartura d.d.
Lendavska ulica 16a
10000 Zagreb, Croatia
Email: robert.marko@...tura.hr
Web: www.sartura.hr
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