netdev - RE: [Intel-wired-lan] [PATCH iwl-net] ice: fix missing TX timestamps interrupts on E825 devices

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <PH0PR11MB75223BA2F0B80DBE1790B5CAA091A@PH0PR11MB7522.namprd11.prod.outlook.com>
Date: Wed, 28 Jan 2026 19:30:21 +0000
From: "Mekala, SunithaX D" <sunithax.d.mekala@...el.com>
To: "Nitka, Grzegorz" <grzegorz.nitka@...el.com>,
	"intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>
CC: "Loktionov, Aleksandr" <aleksandr.loktionov@...el.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>, "Nguyen, Anthony L"
	<anthony.l.nguyen@...el.com>, "Kitszel, Przemyslaw"
	<przemyslaw.kitszel@...el.com>
Subject: RE: [Intel-wired-lan] [PATCH iwl-net] ice: fix missing TX timestamps
 interrupts on E825 devices

> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@...osl.org> On Behalf Of Grzegorz Nitka
> Sent: Thursday, November 27, 2025 1:26 AM
> To: intel-wired-lan@...ts.osuosl.org
> Cc: Loktionov, Aleksandr <aleksandr.loktionov@...el.com>; netdev@...r.kernel.org; Nguyen, Anthony L <anthony.l.nguyen@...el.com>; Kitszel, Przemyslaw > <przemyslaw.kitszel@...el.com>
> Subject: [Intel-wired-lan] [PATCH iwl-net] ice: fix missing TX timestamps interrupts on E825 devices
>
> Modify PTP (Precision Time Protocol) configuration on link down flow.
> Previously, PHY_REG_TX_OFFSET_READY register was cleared in such case.
> This register is used to determine if the timestamp is valid or not on
> the hardware side.
> However, there is a possibility that there is still the packet in the
> HW queue which originally was supposed to be timestamped but the link
> is already down and given register is cleared.
> This potentially might lead to the situation in which that 'delayed'
> packet's timestamp is treated as invalid one when the link is up
> again.
> This in turn leads to the situation in which the driver is not able to
> effectively clean timestamp memory and interrupt configuration.
> From the hardware perspective, that 'old' interrupt was not handled
> properly and even if new timestamp packets are processed, no new
> interrupts is generated. As a result, providing timestamps to the user
> applications (like ptp4l) is not possible.
> The solution for this problem is implemented at the driver level rather
> than the firmware, and maintains the tx_ready bit high, even during
> link down events. This avoids entering a potential inconsistent state
> between the driver and the timestamp hardware.
>
> Testing hints:
> - run PTP traffic at higher rate (like 16 PTP messages per second)
> - observe ptp4l behaviour at the client side in the following
>  conditions:
>	a) trigger link toggle events. It needs to be physiscal
>            link down/up events
>	b) link speed change
> In all above cases, PTP processing at ptp4l application should resume
> always. In failure case, the following permanent error message in ptp4l
> log was observed:
> controller-0 ptp4l: err [6175.116] ptp4l-legacy timed out while polling
>	for tx timestamp
>
> Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
> Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@...el.com>
> Signed-off-by: Grzegorz Nitka <grzegorz.nitka@...el.com>
> ---
> drivers/net/ethernet/intel/ice/ice_ptp.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)

Tested-by: Sunitha Mekala <sunithax.d.mekala@...el.com> (A Contingent worker at Intel)