[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <9dfdeee0-7758-439b-a2a5-a7f243427cf4@bootlin.com>
Date: Fri, 30 Jan 2026 18:29:23 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>,
Andrew Lunn <andrew@...n.ch>
Cc: Alexandre Torgue <alexandre.torgue@...s.st.com>,
Andrew Lunn <andrew+netdev@...n.ch>, "David S. Miller"
<davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, linux-arm-kernel@...ts.infradead.org,
linux-stm32@...md-mailman.stormreply.com, netdev@...r.kernel.org,
Paolo Abeni <pabeni@...hat.com>
Subject: Re: [PATCH net-next 1/3] net: stmmac: clear half-duplex caps where
unsupported
Hi,
On 30/01/2026 12:10, Russell King (Oracle) wrote:
> Where a core supports hardware features, but does not indicate support
> for half-duplex, clear phylink's half-duplex 1G, 100M and 10M
> capability bits to disallow half-duplex operation and advertisement of
> these link modes.
>
> This will avoid the need for special code in the PCS driver to do this
> based on the ESTATUS register bits, as the support in the PCS is
> dependent on the same synthesis choice as the MAC core.
>
> Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
Gave it a quick test on socfpga, as this impacts all variants,
and we seem to be good so,
Tested-by: Maxime Chevallier <maxime.chevallier@...tlin.com>
Reviewed-by: Maxime Chevallier <maxime.chevallier@...tlin.com>
Maxime
Powered by blists - more mailing lists