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Date: Thu, 27 Feb 2014 20:45:49 -0500
From: Bill Cox <waywardgeek@...il.com>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] die area estimates (Re: [PHC] GPU multiplication speed?)

On Thu, Feb 27, 2014 at 11:36 AM, Solar Designer <solar@...nwall.com> wrote:
> On Thu, Feb 27, 2014 at 08:15:51PM +0400, Solar Designer wrote:
>> If we estimate 1 bit of SRAM to be roughly the same as a 1-bit full
>> adder
>
> Wikipedia gives 6 transistors for 1 bit of SRAM vs. 28 for 1 full adder:
>
> http://en.wikipedia.org/wiki/Transistor_count

This sounds about right to me.  Also, the 28 for the full adder will
not layout quite as nicely.

> The smallest full adder I heard of (half-analog, weird) is 4 transistors
> plus 4 diodes (and other components):
>
> http://3.14.by/en/read/BarsFA-4T-full-adder
>
> It's probably not suitable for high-speed ASIC.  (I'm toying with the
> idea of actually trying it on a breadboard.)
>
> Using canonical estimates for transistor count, a 32x32->64 multiplier
> is more like a 4 KiB SRAM.
>
> Alexander

In the logic cells I designed for ViASIC, we had 16 6-T SRAM cells, 4
NAND gates, a DFF, 2 MUXes, and a few inverters.  I'd guess I could
build a custom carry-save adder in the space of the 4 NAND gates,
another in the mux area, and a couple in the flop.  Roughly a 4-to-1
ratio which seems about right, especially when you take the decoders
and read circuits into account.  Maybe 5-to-1, which is in line with
the estimate above.

With 4-to-1, and just a carry-save multiplier, I'd get 32x32x4 = 4K
bits... but you ware saying bytes, right?  Are we having a big-B
little-b communication thing?  I hate those...

Bill

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