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Date: Fri, 04 Apr 2014 21:46:41 +0100
From: Samuel Neves <>
Subject: Re: [PHC] Gambit review

On 04-04-2014 21:37, Bill Cox wrote:
> Now that I've seen a couple entries that use the new AESENC
> instruction, I'm more of a fan.  It has a 2 cycle latency, and the CPU
> can queue a sick number of them per core, like 8.  

Just a bit of pedantry: the best latency for AESENC I know of is 7 cycles on Haswell. You can dispatch 1 every cycle
(per core) in every chip, though. What this roughly means is that you can perform ~7-8 parallel AES encryptions for the
cost of one.

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