phc-discussions - Re: [PHC] Chip size

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Message-ID: <20150112230325.GA30256@bolet.org>
Date: Tue, 13 Jan 2015 00:03:25 +0100
From: Thomas Pornin <pornin@...et.org>
To: discussions@...sword-hashing.net
Subject: Re: [PHC] Chip size

On Mon, Jan 12, 2015 at 08:41:24PM +0000, Marsh Ray wrote:
> If you look closely, you can see that this wafer is not an array of
> smaller chips. It is *one big circuit*, possibly some kind of CCD
> imager for a telescope or imaging satellite.
> 
> Of course, such a large circuit is likely to result in a low yield,
> which perhaps explains how they ended up in the kitsch supply chain.
> But it is an existence proof that wafer-sized circuits are possible,
> modulo thermal solutions.

Note that CCD imagers are tolerant to small defects. A typical CCD will
feature a few bad pixels (possibly even a full bad line), for whom the
value will be interpolated from adjacent pixels.

What makes chip cost rise faster-than-linearly with area is defects; a
larger chip increases the probability that it will include a local
defect, and a chip with a defect is ditched entirely (this is the part
where things are not linear). If the chip design is tolerant to defects
(to some extent), then it can be substantially cheaper; CCD are in that
case.

	--Thomas Pornin