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Message-ID: <Pine.LNX.4.64.0701171445120.18888@localhost.localdomain>
Date:	Wed, 17 Jan 2007 14:46:01 -0500 (EST)
From:	Chip Coldwell <coldwell@...hat.com>
To:	Chip Coldwell <coldwell@...hat.com>
cc:	Andi Kleen <ak@...e.de>, Chris Wedgwood <cw@...f.org>,
	Christoph Anton Mitterer <calestyo@...entia.net>,
	Robert Hancock <hancockr@...w.ca>,
	linux-kernel@...r.kernel.org, knweiss@....de,
	andersen@...epoet.org, krader@...ibm.com, lfriedman@...dia.com,
	linux-nforce-bugs@...dia.com
Subject: Re: data corruption with nvidia chipsets and IDE/SATA drives (k8
 cpu errata needed?)

On Wed, 17 Jan 2007, Chip Coldwell wrote:

> On Wed, 17 Jan 2007, Andi Kleen wrote:
>
>> On Wednesday 17 January 2007 07:31, Chris Wedgwood wrote:
>>> On Tue, Jan 16, 2007 at 08:52:32PM +0100, Christoph Anton Mitterer wrote:
>>>> I agree,... it seems drastic, but this is the only really secure
>>>> solution.
>>> 
>>> I'd like to here from Andi how he feels about this?  It seems like a
>>> somewhat drastic solution in some ways given a lot of hardware doesn't
>>> seem to be affected (or maybe in those cases it's just really hard to
>>> hit, I don't know).
>> 
>> AMD is looking at the issue. Only Nvidia chipsets seem to be affected,
>> although there were similar problems on VIA in the past too.
>> Unless a good workaround comes around soon I'll probably default
>> to iommu=soft on Nvidia.
>> 
>
> We've just verified that configuring the graphics aperture to be
> write-combining instead of write-back using an MTRR also solves the
> problem.  It appears to be a cache incoherency issue in the graphics
> aperture.

I take it back.  Further testing has revealed that this does not solve
the problem.

Chip

-- 
Charles M. "Chip" Coldwell
Senior Software Engineer
Red Hat, Inc
978-392-2426

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