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Message-ID: <7c86c4470803071301n553273a8t231534ffce51b8b5@mail.gmail.com> Date: Fri, 7 Mar 2008 13:01:18 -0800 From: "stephane eranian" <eranian@...glemail.com> To: "Robert Richter" <robert.richter@....com> Cc: linux-kernel@...r.kernel.org, akpm@...ux-foundation.org, ak@...e.de Subject: Re: [PATCH 2/3] perfmon x86 infrastructure definitions Robert, On Fri, Mar 7, 2008 at 3:42 AM, Robert Richter <robert.richter@....com> wrote: > > On 06.03.08 22:25:26, stephane eranian wrote: > > adds AMD Northbridge config MSR definition > > > > Signed-off-by: Stephane Eranian <eranian@...il.com> > > Signed-off-by: Robert Richter <robert.richter@....com> > > > --- a/include/asm-x86/msr-index.h > > +++ b/include/asm-x86/msr-index.h > > @@ -83,6 +83,7 @@ > > /* AMD64 MSRs. Not complete. See the architecture manual for a more > > complete list. */ > > > > +#define MSR_AMD64_NB_CFG 0xc001001f > > This will probably not be needed after mm config works fine (patches > from Yinghai Lu). Since the usage of CF8 extended configuration cycles > is not recommended, the current code to enable IBS interrupts can be > seen as temporary. I will rework the IBS code so that it uses mm > config. > Ok, but I want to push what we have now. We can change this later. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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