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Message-Id: <1212475730.9496.30.camel@pasglop>
Date: Tue, 03 Jun 2008 16:48:50 +1000
From: Benjamin Herrenschmidt <benh@...nel.crashing.org>
To: Nick Piggin <nickpiggin@...oo.com.au>
Cc: Russell King <rmk+lkml@....linux.org.uk>,
Linus Torvalds <torvalds@...ux-foundation.org>,
David Miller <davem@...emloft.net>, linux-arch@...r.kernel.org,
scottwood@...escale.com, linuxppc-dev@...abs.org,
alan@...rguk.ukuu.org.uk, linux-kernel@...r.kernel.org,
tpiepho@...escale.com
Subject: Re: MMIO and gcc re-ordering issue
On Tue, 2008-06-03 at 16:11 +1000, Nick Piggin wrote:
> > - readl is synchronous (ie, makes the CPU think the
> > data was actually used before executing subsequent
> > instructions, thus waits for the data to come back,
> > for example to ensure that a read used to push out
> > post buffers followed by a delay will indeed happen
> > with the right delay).
>
> So your readl can pass an earlier cacheable store or earlier writel?
I forgot to mention that all MMIO are ordered vs. each other and I
do prevent readl from passing earlier cacheable stores too in my
current implementation but I'n not 100% we want to "guarantee" that,
unless we have stupid devices that trigger DMA's on reads with side
effects.. anyway, it is guaranteed in the current case.
Ben.
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