linux-kernel - Re: [PATCH 1/4] perf, x86: Add Intel Nehalem/Westmere uncore pmu

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Message-ID: <1309864954.3282.61.camel@twins>
Date:	Tue, 05 Jul 2011 13:22:34 +0200
From:	Peter Zijlstra <a.p.zijlstra@...llo.nl>
To:	Andi Kleen <andi@...stfloor.org>
Cc:	Lin Ming <ming.m.lin@...el.com>, Ingo Molnar <mingo@...e.hu>,
	Stephane Eranian <eranian@...gle.com>,
	Arnaldo Carvalho de Melo <acme@...stprotocols.net>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/4] perf, x86: Add Intel Nehalem/Westmere uncore pmu

On Mon, 2011-07-04 at 23:57 +0200, Andi Kleen wrote:
> > > There are no NMIs without sampling, so at least the comment seems bogus.
> > > Perhaps the code could be a bit simplified now without atomics.
> > 
> > I'm not sure if uncore PMU interrupt need to be enabled for counting
> > only. What do you think?
> 
> Only for overflow handling to accumulate into a larger counter, but it doesn't 
> need to be an NMI for that.

Uncore is hooked into the regular PMI, and since we wire that to the NMI
the uncore will always be NMI too.

>   But it's not strictly required I would say, 
> 44(?) bits are probably enough for near all use cases.

44bits is in the hours range for pure cycle counts, which is so-so. I
bet you're going to be very annoyed when you find your counters are
wrecked after your 5 hour test run finishes.
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