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Message-ID: <alpine.DEB.2.00.1108251206440.27407@router.home>
Date: Thu, 25 Aug 2011 12:07:44 -0500 (CDT)
From: Christoph Lameter <cl@...ux.com>
To: James Bottomley <James.bottomley@...senPartnership.com>
cc: Peter Zijlstra <peterz@...radead.org>,
Andrew Morton <akpm@...ux-foundation.org>,
Greg Thelen <gthelen@...gle.com>, linux-kernel@...r.kernel.org,
linux-mm@...ck.org,
KAMEZAWA Hiroyuki <kamezawa.hiroyu@...fujitsu.com>,
Balbir Singh <bsingharora@...il.com>,
Daisuke Nishimura <nishimura@....nes.nec.co.jp>,
linux-arch@...r.kernel.org
Subject: Re: [PATCH] memcg: remove unneeded preempt_disable
On Thu, 25 Aug 2011, James Bottomley wrote:
> >ARM seems to have these LDREX/STREX instructions for that purpose which
> >seem to be used for generating atomic instructions without lockes. I
> >guess
> >other RISC architectures have similar means of doing it?
>
> Arm isn't really risc. Most don't. However even with ldrex/strex you need two instructions for rmw.
Well then what is "really risc"? RISC is an old beaten down marketing term
AFAICT and ARM claims it too.
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