linux-kernel - Re: [PATCH] Use correct byte-sized register constraint in __xchg

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Message-ID: <4F7E9F3E.3050301@goop.org>
Date:	Fri, 06 Apr 2012 00:46:06 -0700
From:	Jeremy Fitzhardinge <jeremy@...p.org>
To:	the arch/x86 maintainers <x86@...nel.org>
CC:	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	Thomas Reitmayr <treitmayr@...base.at>,
	leigh123linux@...glemail.com, Dave Jones <davej@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>, Ingo Molnar <mingo@...e.hu>,
	Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH] Use correct byte-sized register constraint in __xchg_op()

PIng?

On 04/02/2012 04:15 PM, Jeremy Fitzhardinge wrote:
> x86-64 can access the low half of any register, but i386 can only do
> it with a subset of registers.  'r' causes compilation failures on i386,
> but 'q' expresses the constraint properly.
>
> Signed-off-by: Jeremy Fitzhardinge <jeremy@...p.org>
> Reported-by: Leigh Scott <leigh123linux@...glemail.com>
> Tested-by: Thomas Reitmayr <treitmayr@...base.at>
>
> diff --git a/arch/x86/include/asm/cmpxchg.h b/arch/x86/include/asm/cmpxchg.h
> index b3b7332..bc18d0e 100644
> --- a/arch/x86/include/asm/cmpxchg.h
> +++ b/arch/x86/include/asm/cmpxchg.h
> @@ -43,7 +43,7 @@ extern void __add_wrong_size(void)
>  		switch (sizeof(*(ptr))) {				\
>  		case __X86_CASE_B:					\
>  			asm volatile (lock #op "b %b0, %1\n"		\
> -				      : "+r" (__ret), "+m" (*(ptr))	\
> +				      : "+q" (__ret), "+m" (*(ptr))	\
>  				      : : "memory", "cc");		\
>  			break;						\
>  		case __X86_CASE_W:					\
>
>
> --
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