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Message-ID: <20120627145831.GF20638@somewhere.redhat.com>
Date: Wed, 27 Jun 2012 16:58:34 +0200
From: Frederic Weisbecker <fweisbec@...il.com>
To: Jiri Olsa <jolsa@...hat.com>
Cc: acme@...hat.com, a.p.zijlstra@...llo.nl, mingo@...e.hu,
paulus@...ba.org, cjashfor@...ux.vnet.ibm.com, eranian@...gle.com,
gorcunov@...nvz.org, tzanussi@...il.com, mhiramat@...hat.com,
robert.richter@....com, fche@...hat.com,
linux-kernel@...r.kernel.org, masami.hiramatsu.pt@...achi.com,
drepper@...il.com, asharma@...com, benjamin.redelings@...cent.org
Subject: Re: [PATCH 02/23] perf: Unified API to record selective sets of arch
registers
On Wed, Jun 20, 2012 at 07:39:00PM +0200, Jiri Olsa wrote:
> On Wed, Jun 20, 2012 at 06:42:36PM +0200, Frederic Weisbecker wrote:
> > On Tue, Jun 19, 2012 at 05:47:53PM +0200, Jiri Olsa wrote:
>
> SNIP
>
> > > diff --git a/arch/x86/include/asm/perf_regs.h b/arch/x86/include/asm/perf_regs.h
> > > new file mode 100644
> > > index 0000000..0397bfc
> > > --- /dev/null
> > > +++ b/arch/x86/include/asm/perf_regs.h
> > > @@ -0,0 +1,34 @@
> > > +#ifndef _ASM_X86_PERF_REGS_H
> > > +#define _ASM_X86_PERF_REGS_H
> > > +
> > > +enum perf_event_x86_regs {
> > > + PERF_REG_X86_AX,
> > > + PERF_REG_X86_BX,
> > > + PERF_REG_X86_CX,
> > > + PERF_REG_X86_DX,
> > > + PERF_REG_X86_SI,
> > > + PERF_REG_X86_DI,
> > > + PERF_REG_X86_BP,
> > > + PERF_REG_X86_SP,
> > > + PERF_REG_X86_IP,
> > > + PERF_REG_X86_FLAGS,
> > > + PERF_REG_X86_CS,
> > > + PERF_REG_X86_DS,
> > > + PERF_REG_X86_ES,
> > > + PERF_REG_X86_FS,
> > > + PERF_REG_X86_GS,
> > > + PERF_REG_X86_R8,
> > > + PERF_REG_X86_R9,
> > > + PERF_REG_X86_R10,
> > > + PERF_REG_X86_R11,
> > > + PERF_REG_X86_R12,
> > > + PERF_REG_X86_R13,
> > > + PERF_REG_X86_R14,
> > > + PERF_REG_X86_R15,
> > > + PERF_REG_X86_SS,
> > > +
> > > + /* non ABI */
> > > + PERF_REG_X86_64_MAX = PERF_REG_X86_SS + 1,
> >
> > SS also exist in 32 bits, right?
> > Although I guess userspace doesn't care much.
>
> yes it's there
But PERF_REG_X86_SS is above PERF_REG_X86_32_MAX.
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