linux-kernel - RE: [PATCH 2/2] PCI: fix system hang issue of Marvell SATA host controller

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Message-ID: <F766E4F80769BD478052FB6533FA745D25F440ACE9@SC-VEXCH4.marvell.com>
Date:	Wed, 13 Mar 2013 02:40:07 -0700
From:	Xiangliang Yu <yuxiangl@...vell.com>
To:	Bjorn Helgaas <bhelgaas@...gle.com>
CC:	Myron Stowe <myron.stowe@...il.com>, yxlraid <yxlraid@...il.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH 2/2] PCI: fix system hang issue of Marvell SATA host
 controller

Hi, Bjorn

> >> > Now, the situation is like this:
> >> > I captured the PCIE trace with analyzer and found that 1st BE is 0x1111
> >> > when
> >> > accessing IO port space. But 9125 spec has some limitation, and the BE
> >> > must
> >> > be
> >> > 0x0100, to access the 2nd byte only. So, the chip will go to bad.
> >>
> >> Great, this is new, interesting, data.  Is the 9125 spec publicly
> >> accessible and/or could you elaborate on the "some limitation"
> >> comment?
> > 9125 spec is publicly accessible.
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