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Date: Thu, 12 Jun 2014 18:19:19 +0800 From: Jisheng Zhang <jszhang@...vell.com> To: Russell King - ARM Linux <linux@....linux.org.uk> CC: "robh+dt@...nel.org" <robh+dt@...nel.org>, "pawel.moll@....com" <pawel.moll@....com>, "mark.rutland@....com" <mark.rutland@....com>, "ijc+devicetree@...lion.org.uk" <ijc+devicetree@...lion.org.uk>, "galak@...eaurora.org" <galak@...eaurora.org>, "sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>, "alexandre.belloni@...e-electrons.com" <alexandre.belloni@...e-electrons.com>, "antoine.tenart@...e-electrons.com" <antoine.tenart@...e-electrons.com>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org> Subject: Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency as 2 cycles Hi Russell, On Thu, 12 Jun 2014 03:15:03 -0700 Jisheng Zhang <jszhang@...vell.com> wrote: > Hi Russell, > > On Thu, 12 Jun 2014 02:44:23 -0700 > Russell King - ARM Linux <linux@....linux.org.uk> wrote: > > > On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote: > > > For all BG2Q SoCs, 2 cycles is the best/correct value > > > > It would be a good idea to set all these parameters if you need to set > > them at all - in other words, setting arm,dirty-latency as well, as > > that's all part of the timing specification. > > > > Thanks for reviewing this patch. I will check with SoC people to find the > correct dirty-latency value. The BG2Q L2 cache controller is PL310, so no "dirty-latency" Thanks, Jisheng -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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