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Message-ID: <20140612181503.06562a38@xhacker>
Date: Thu, 12 Jun 2014 18:15:03 +0800
From: Jisheng Zhang <jszhang@...vell.com>
To: Russell King - ARM Linux <linux@....linux.org.uk>
CC: "robh+dt@...nel.org" <robh+dt@...nel.org>,
"pawel.moll@....com" <pawel.moll@....com>,
"mark.rutland@....com" <mark.rutland@....com>,
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<alexandre.belloni@...e-electrons.com>,
"antoine.tenart@...e-electrons.com"
<antoine.tenart@...e-electrons.com>,
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<linux-arm-kernel@...ts.infradead.org>,
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Subject: Re: [PATCH] ARM: dts: berlin2q.dtsi: set L2CC tag and data latency
as 2 cycles
Hi Russell,
On Thu, 12 Jun 2014 02:44:23 -0700
Russell King - ARM Linux <linux@....linux.org.uk> wrote:
> On Thu, Jun 12, 2014 at 05:38:40PM +0800, Jisheng Zhang wrote:
> > For all BG2Q SoCs, 2 cycles is the best/correct value
>
> It would be a good idea to set all these parameters if you need to set
> them at all - in other words, setting arm,dirty-latency as well, as
> that's all part of the timing specification.
>
Thanks for reviewing this patch. I will check with SoC people to find the correct
dirty-latency value.
Thanks,
Jisheng
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