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Message-ID: <CA+mB=1+4=eG6d-99+yZ6HgpqvU2uan+-13pXt1=H+GZ0HeRL1A@mail.gmail.com>
Date:	Thu, 27 Nov 2014 12:19:26 +0530
From:	Srikanth Thokala <sriku.linux@...il.com>
To:	Jonathan Corbet <corbet@....net>
Cc:	linux-doc@...r.kernel.org,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Srikanth Thokala <sriku.linux@...il.com>
Subject: Re: [PATCH] Documentation: memory-barriers: Fix typo in the first example

Hi,

Kindly review the patch.

Thanks
Srikanth

On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
<sriku.linux@...il.com> wrote:
> In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
> match the sequence of events described below it.  To match the
> sequence of events, the values of 'A' and 'B' should be loaded
> into 'x' and 'y' respectively.
>
> Signed-off-by: Srikanth Thokala <sriku.linux@...il.com>
> ---
>  Documentation/memory-barriers.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> index 22a969c..2770bce 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -115,8 +115,8 @@ For example, consider the following sequence of events:
>         CPU 1           CPU 2
>         =============== ===============
>         { A == 1; B == 2 }
> -       A = 3;          x = B;
> -       B = 4;          y = A;
> +       A = 3;          x = A;
> +       B = 4;          y = B;
>
>  The set of accesses as seen by the memory system in the middle can be arranged
>  in 24 different combinations:
> --
> 1.9.1
>
--
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