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Message-ID: <20150114211434.GT16533@saruman>
Date:	Wed, 14 Jan 2015 15:14:34 -0600
From:	Felipe Balbi <balbi@...com>
To:	Alan Stern <stern@...land.harvard.edu>
CC:	Felipe Balbi <balbi@...com>,
	Robert Baldyga <r.baldyga@...sung.com>, <paulz@...opsys.com>,
	<gregkh@...uxfoundation.org>, <linux-usb@...r.kernel.org>,
	<linux-kernel@...r.kernel.org>, <dinguyen@...nsource.altera.com>,
	<yousaf.kaukab@...el.com>, <m.szyprowski@...sung.com>
Subject: Re: [PATCH v2] usb: dwc2: call dwc2_is_controller_alive() under
 spinlock

Hi,

On Wed, Jan 14, 2015 at 03:06:39PM -0500, Alan Stern wrote:
> > > This patch fixes bug described here:
> > > https://lkml.org/lkml/2014/12/22/185
> > > 
> > > Signed-off-by: Robert Baldyga <r.baldyga@...sung.com>
> > > ---
> > > 
> > > Changelog:
> > > 
> > > v2:
> > > - fixed comment from Paul Zimmerman
> > > 
> > > v1: https://lkml.org/lkml/2015/1/13/186
> > > 
> > >  drivers/usb/dwc2/core_intr.c | 6 +++---
> > >  1 file changed, 3 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c
> > > index ad43c5b..02e3e2d 100644
> > > --- a/drivers/usb/dwc2/core_intr.c
> > > +++ b/drivers/usb/dwc2/core_intr.c
> > > @@ -476,13 +476,13 @@ irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
> > >  	u32 gintsts;
> > >  	irqreturn_t retval = IRQ_NONE;
> > >  
> > > +	spin_lock(&hsotg->lock);
> > > +
> > >  	if (!dwc2_is_controller_alive(hsotg)) {
> > 
> > This is really, really odd. Register accesses are atomic, so the lock
> > isn't really doing anything. Besides, you're calling
> > dwc2_is_controller_alive() from within the IRQ handler, so IRQs are
> > already disabled.
> 
> Spinlocks sometimes do more than you think.  For instance, here the 
> lock prevents the register access from happening while some other CPU 
> is holding the lock.  If a silicon quirk causes the register access to 
> interfere with other activities, this could be important.

readl() (which is used by dwc2_is_controller_alive()) adds a memory
barrier to the register accesses, that should force all register
accesses the be correctly ordered. I fail to see how a silicon quirk
could cause this and if, indeed, it does, I'd be more comfortable with a
proper STARS tickect number from synopsys :-s

Then again, I don't even have a device with this controller and it seems
to only be a problem with Robert's setup, so maybe it's a silicon bug
caused by whoever integrated dwc2 in his silicon.

-- 
balbi

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