linux-kernel - Re: futex atomic vs ordering constraints

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Message-ID: <55E9D423.1090803@ezchip.com>
Date:	Fri, 4 Sep 2015 13:25:55 -0400
From:	Chris Metcalf <cmetcalf@...hip.com>
To:	Linus Torvalds <torvalds@...ux-foundation.org>,
	Peter Zijlstra <peterz@...radead.org>
CC:	Thomas Gleixner <tglx@...utronix.de>,
	Will Deacon <will.deacon@....com>,
	Oleg Nesterov <oleg@...hat.com>,
	Paul McKenney <paulmck@...ux.vnet.ibm.com>,
	Ingo Molnar <mingo@...nel.org>,
	"mtk.manpages@...il.com" <mtk.manpages@...il.com>,
	"dvhart@...radead.org" <dvhart@...radead.org>,
	"dave@...olabs.net" <dave@...olabs.net>,
	"Vineet.Gupta1@...opsys.com" <Vineet.Gupta1@...opsys.com>,
	"ralf@...ux-mips.org" <ralf@...ux-mips.org>,
	"ddaney@...iumnetworks.com" <ddaney@...iumnetworks.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Russell King - ARM Linux <linux@....linux.org.uk>,
	Richard Henderson <rth@...ddle.net>
Subject: Re: futex atomic vs ordering constraints

On 09/02/2015 05:18 PM, Linus Torvalds wrote:
> For example, on x86, the locked instructions are obviously already
> sufficiently strong, but even if they weren't, kernel entry/exit is
> documented to be a serializing instruction (which is something
> insanely much stronger than just memory ordering). And I suspect there
> are similar issues on a lot of architectures where the memory ordering
> is done by the core, but the cache subsystem is strongly ordered (ie
> saen good SMP systems - so it sounds like tile needs the smp_mb()'s,
> but I would almost suspect that POWER and ARM might *not* need them).

Because POWER and ARM have serializing kernel entry/exit?
I think tile has relatively conventional cache/memory semantics,
but it's certainly true there is implicit memory ordering guarantee
for kernel entry/exit.

-- 
Chris Metcalf, EZChip Semiconductor
http://www.ezchip.com

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