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Message-ID: <CAGVrzca34xrVznoEE2e26JyR11Q9L1sT4mJcNZ=NuprqUnZnjw@mail.gmail.com>
Date:	Mon, 9 Nov 2015 18:29:11 -0800
From:	Florian Fainelli <f.fainelli@...il.com>
To:	Linus Walleij <linus.walleij@...aro.org>
Cc:	Kapil Hali <kapilh@...adcom.com>, Rob Herring <robh+dt@...nel.org>,
	Pawel Moll <pawel.moll@....com>,
	Mark Rutland <mark.rutland@....com>,
	Ian Campbell <ijc+devicetree@...lion.org.uk>,
	Kumar Gala <galak@...eaurora.org>,
	Russell King <linux@....linux.org.uk>,
	Ray Jui <rjui@...adcom.com>,
	Scott Branden <sbranden@...adcom.com>,
	Jon Mason <jonmason@...adcom.com>,
	Gregory Fong <gregory.0xf0@...il.com>,
	Lee Jones <lee@...nel.org>, Hauke Mehrtens <hauke@...ke-m.de>,
	Heiko Stuebner <heiko@...ech.de>,
	Kever Yang <kever.yang@...k-chips.com>,
	Maxime Ripard <maxime.ripard@...e-electrons.com>,
	Olof Johansson <olof@...om.net>,
	Paul Walmsley <paul@...an.com>, Chen-Yu Tsai <wens@...e.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	bcm-kernel-feedback-list <bcm-kernel-feedback-list@...adcom.com>
Subject: Re: [PATCH RESEND v2 3/4] ARM: BCM: Add SMP support for Broadcom NSP

2015-11-09 2:09 GMT-08:00 Linus Walleij <linus.walleij@...aro.org>:
> On Fri, Nov 6, 2015 at 8:49 PM, Kapil Hali <kapilh@...adcom.com> wrote:
>
>> Add SMP support for Broadcom's Northstar Plus SoC
>> cpu enable method. This changes also consolidates
>> iProc family's - BCM NSP and BCM Kona, platform
>> SMP handling in a common file.
>>
>> Northstar Plus SoC is based on ARM Cortex-A9
>> revision r3p0 which requires configuration for ARM
>> Errata 764369 for SMP. This change adds the needed
>> configuration option.
>>
>> Signed-off-by: Kapil Hali <kapilh@...adcom.com>
>
> This version looks saner to me.
>
>> +static int nsp_write_lut(void)
>> +{
>> +       void __iomem *sku_rom_lut;
>> +       phys_addr_t secondary_startup_phy;
>> +
>> +       if (!secondary_boot) {
>> +               pr_warn("required secondary boot register not specified\n");
>> +               return -EINVAL;
>> +       }
>> +
>> +       sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot,
>> +                                               sizeof(secondary_boot));
>
> Why is this address not just taken directly from the device tree?

It comes directly from DT, that's what bcm_smp_prepare_cpus() does
read from Device Tree.

>
> If it is not in the device tree: why?
>
> Also give it a sane name, bcm_sec_boot_address or so.
> "secondary_boot" sounds like a function you call to boot
> the second core.

Agree with that, there could be a better name which better reflects
this is a variable.
-- 
Florian
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