[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <4016576.NEsgSPjyJ9@diego>
Date: Mon, 25 Jan 2016 15:04:31 +0100
From: Heiko Stübner <heiko@...ech.de>
To: kishon@...com
Cc: mturquette@...libre.com, sboyd@...eaurora.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org, dianders@...omium.org,
romain.perier@...il.com, arnd@...db.de, hl@...k-chips.com
Subject: Re: [PATCH v3 7/8] clk: rockchip: fix usbphy-related clocks
Kishon,
Am Donnerstag, 19. November 2015, 22:22:28 schrieb Heiko Stuebner:
> The otgphy clocks really only drive the phy blocks. These in turn
> contain plls that then generate the 480m clocks the clock controller
> uses to supply some other clocks like uart0, gpu or the video-codec.
>
> So fix this structure to actually respect that hirarchy and removed
> that usb480m fixed-rate clock working as a placeholder till now, as
> this wouldn't even work if the supplying phy gets turned off while
> its pll-output gets used elsewhere.
>
> Signed-off-by: Heiko Stuebner <heiko@...ech.de>
> Reviewed-by: Douglas Anderson <dianders@...omium.org>
it looks like this patch didn't make your cutoff time for sending your stuff
to Greg. As the core phy series up to patch 5 is in mainline now, I've just
applied this patch to my clk-branch for 4.6.
Heiko
Powered by blists - more mailing lists