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Date: Thu, 28 Jan 2016 14:32:13 +0800 From: Shawn Guo <shawnguo@...nel.org> To: Carlos Soto <csotoalonso@...il.com> Cc: Sascha Hauer <kernel@...gutronix.de>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...eaurora.org>, linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH 1/1] imx25: Fix LCD pixelclock configuration On Wed, Dec 23, 2015 at 09:30:10PM +0100, Carlos Soto wrote: > Set LCDC base clock (per_7) parent clock to UPLL clock. > This is needed to allow finer resolution in pixelclock > > Signed-off-by: Carlos Soto <csotoalonso@...il.com> > --- > drivers/clk/imx/clk-imx25.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c > index c4c141c..656340e 100644 > --- a/drivers/clk/imx/clk-imx25.c > +++ b/drivers/clk/imx/clk-imx25.c > @@ -238,6 +238,12 @@ static int __init __mx25_clocks_init(unsigned long osc_rate, > clk_set_parent(clk[per5_sel], clk[ahb]); > > /* > + * set LCDC base clock (per 7) to highest possible frequency (UPLL) > + * to get best resolution for pixel clock > + */ > + clk_set_parent(clk[per7_sel], clk[upll]); This can be done in device tree via assigned-clock-parents without the need of touching kernel. Shawn > + > + /* > * Let's initially set up CLKO parent as ipg, since this configuration > * is used on some imx25 board designs to clock the audio codec. > */ > -- > 1.7.10.4 > >
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