linux-kernel - Re: [PATCH 3/3] irqchip: mips-gic: Setup EIC mode on each CPU if it's in use

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <573C1191.80707@imgtec.com>
Date:	Wed, 18 May 2016 07:54:09 +0100
From:	Matt Redfearn <matt.redfearn@...tec.com>
To:	Paul Burton <paul.burton@...tec.com>, <linux-mips@...ux-mips.org>,
	"Ralf Baechle" <ralf@...ux-mips.org>
CC:	Marc Zyngier <marc.zyngier@....com>,
	Jason Cooper <jason@...edaemon.net>,
	Thomas Gleixner <tglx@...utronix.de>,
	<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] irqchip: mips-gic: Setup EIC mode on each CPU if it's
 in use



On 17/05/16 15:31, Paul Burton wrote:
> When EIC mode is in use (cpu_has_veic is true) enable it on each CPU
> during GIC initialisation. Otherwise there may be a mismatch between the
> hardware default interrupt model & that expected by the kernel.
>
> Signed-off-by: Paul Burton <paul.burton@...tec.com>
> ---
>
>   drivers/irqchip/irq-mips-gic.c | 10 +++++++++-
>   1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
> index 4dffccf..bc23c92 100644
> --- a/drivers/irqchip/irq-mips-gic.c
> +++ b/drivers/irqchip/irq-mips-gic.c
> @@ -956,7 +956,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
>   			      unsigned int cpu_vec, unsigned int irqbase,
>   			      struct device_node *node)
>   {
> -	unsigned int gicconfig;
> +	unsigned int gicconfig, cpu;
>   	unsigned int v[2];
>   
>   	__gic_base_addr = gic_base_addr;
> @@ -973,6 +973,14 @@ static void __init __gic_init(unsigned long gic_base_addr,
>   	gic_vpes = gic_vpes + 1;
>   
>   	if (cpu_has_veic) {
> +		/* Set EIC mode for all VPEs */
> +		for_each_present_cpu(cpu) {
> +			gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
> +				  mips_cm_vp_id(cpu));
> +			gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
> +				  GIC_VPE_CTL_EIC_MODE_MSK);
> +		}
> +
>   		/* Always use vector 1 in EIC mode */
>   		gic_cpu_pin = 0;
>   		timer_cpu_pin = gic_cpu_pin;
Hi Paul

Reviewed-by: Matt Redfearn <matt.redfearn@...tec.com>
Tested-by: Matt Redfearn <matt.redfearn@...tec.com>

Thanks,
Matt