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Message-ID: <20170728183321.GG2146@codeaurora.org>
Date: Fri, 28 Jul 2017 11:33:21 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: Abhishek Sahu <absahu@...eaurora.org>
Cc: mturquette@...libre.com, andy.gross@...aro.org,
david.brown@...aro.org, rnayak@...eaurora.org,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC 02/12] clk: qcom: flag for 64 bit CONFIG_CTL
On 07/27, Abhishek Sahu wrote:
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 47a1da3..e6cde2d 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -118,7 +118,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> regmap_write(regmap, off + PLL_L_VAL, config->l);
> regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
> regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
> - regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
> +
> + if (pll->flags & SUPPORTS_64BIT_CONFIG_CTL)
> + regmap_write(regmap, off + PLL_CONFIG_CTL_U,
> + config->config_ctl_hi_val);
Is there a hole there? I mean a RAZ/WI register so we can just
keep writing it and not care?
--
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