linux-kernel - Re: [GIT PULL] x86/mm changes for v4.14: PCID support, 5-level paging support, Secure Memory Encryption support

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Message-ID: <20170904122358.uscplql7tzrnimp4@node.shutemov.name>
Date:   Mon, 4 Sep 2017 15:23:58 +0300
From:   "Kirill A. Shutemov" <kirill@...temov.name>
To:     Ingo Molnar <mingo@...nel.org>
Cc:     Linus Torvalds <torvalds@...ux-foundation.org>,
        linux-kernel@...r.kernel.org, Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <hpa@...or.com>,
        Peter Zijlstra <a.p.zijlstra@...llo.nl>,
        Andrew Morton <akpm@...ux-foundation.org>,
        Andy Lutomirski <luto@...nel.org>,
        Borislav Petkov <bp@...en8.de>
Subject: Re: [GIT PULL] x86/mm changes for v4.14: PCID support, 5-level
 paging support, Secure Memory Encryption support

On Mon, Sep 04, 2017 at 11:31:58AM +0200, Ingo Molnar wrote:
> The main changes in this cycle are support for three new, complex hardware 
> features of x86 CPUs:
> 
>  - Add 5-level paging support, which is a new hardware feature on upcoming Intel
>    CPUs allowing up to 128 PB of virtual address space and 4 PB of physical RAM 
>    space - a 256-fold increase over the old limits.

Minor nitpick: I don't see where "256-fold" comes from.

Virtual address space increased from 256 TB to 128 PB -- 512 times.
Physical: 64 TB -> 4 PB -- 64 times.

-- 
 Kirill A. Shutemov