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Message-ID: <1555719.xlEhX7V6v3@diego>
Date: Mon, 18 Sep 2017 13:31:59 +0200
From: Heiko Stübner <heiko@...ech.de>
To: Nickey Yang <nickey.yang@...k-chips.com>
Cc: mark.yao@...k-chips.com, robh+dt@...nel.org, mark.rutland@....com,
airlied@...ux.ie, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
linux-rockchip@...ts.infradead.org, seanpaul@...omium.org,
briannorris@...omium.org, hl@...k-chips.com, zyw@...k-chips.com,
bivvy.bi@...k-chips.com, xbl@...k-chips.com
Subject: Re: [PATCH 5/7] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock
Hi Nickey,
Am Montag, 18. September 2017, 17:05:37 CEST schrieb Nickey Yang:
> clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll
please try to be a bit more verbose in your commit messages :-) .
It looks to me, like this patch does not depend on the other ones and
I can just pick it directly. Correct?
Heiko
> Signed-off-by: Nickey Yang <nickey.yang@...k-chips.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d79e9b3..6aa43fd 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -1629,7 +1629,7 @@
> compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
> reg = <0x0 0xff960000 0x0 0x8000>;
> interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
> + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
> <&cru SCLK_DPHY_TX0_CFG>;
> clock-names = "ref", "pclk", "phy_cfg";
> power-domains = <&power RK3399_PD_VIO>;
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