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Date:   Mon, 16 Oct 2017 17:42:46 +0800
From:   icenowy@...c.io
To:     maxime.ripard@...e-electrons.com
Cc:     Chen-Yu Tsai <wens@...e.org>, David Airlie <airlied@...ux.ie>,
        dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
        linux-sunxi@...glegroups.com
Subject: Re: [linux-sunxi] Re: [PATCH 5/7] drm/sun4i: backend: Offset layer
 buffer address by DRAM starting address

在 2017-10-16 16:00,Maxime Ripard 写道:
> Hi,
> 
> I've applied all the other patches.
> 
> On Sat, Oct 14, 2017 at 12:02:50PM +0800, Chen-Yu Tsai wrote:
>> The display backend, as well as other peripherals that have a DRAM
>> clock gate and access DRAM directly, bypassing the system bus,
>> address the DRAM starting from 0x0, while physical addresses the
>> system uses starts from 0x40000000 (or 0x20000000 in A80's case).
>> 
>> Correct the address configured into the backend layer registers
>> by PHYS_OFFSET to account for this.
> 
> However, I'm a bit confused at this.
> 
> The driver has been working so far, which it wouldn't have been able
> to if the address was wrong. How was this problem noticed, and how can
> that fix not be an issue in itself?

On devices with <=1GiB (0x40000000) DRAM, the DRAM access will just wrap
back and no problem would be seen.

> 
> Thanks!
> Maxime
> 
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

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