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Message-ID: <36810039-168b-9c1f-1be1-491b9b1b4271@redhat.com>
Date: Thu, 30 Nov 2017 13:27:59 +0100
From: Paolo Bonzini <pbonzini@...hat.com>
To: Luwei Kang <luwei.kang@...el.com>, kvm@...r.kernel.org
Cc: tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
x86@...nel.org, rkrcmar@...hat.com, linux-kernel@...r.kernel.org,
joro@...tes.org
Subject: Re: [PATCH v3 0/9] Intel Processor Trace virtulization enabling
On 27/11/2017 21:23, Luwei Kang wrote:
> From v2:
> - replace *_PT_SUPPRESS_PIP to *_PT_CONCEAL_PIP;
> - clean SECONDARY_EXEC_PT_USE_GPA, VM_EXIT_CLEAR_IA32_RTIT_CTL and VM_ENTRY_LOAD_IA32_RTIT_CTL in SYSTEM mode. These bits must be all set or all clean;
> - move processor tracing out of scattered features;
> - add a new function to enable/disable intercept MSRs read/write;
> - add all Intel PT MSRs read/write and disable intercept when PT is enabled in guest;
> - disable Intel PT and enable intercept MSRs when L1 guest VMXON;
> - performance optimization.
> In Host only mode. we just need to save host RTIT_CTL before vm-entry and restore host RTIT_CTL after vm-exit;
> In HOST_GUEST mode. we need to save and restore all MSRs only when PT has enabled in guest.
> - use XSAVES/XRESTORES implement context switch.
> Haven't implementation in this version and still in debuging. will make a separate patch work on this.
That's okay. I have sent a few comments, v4 should be good.
Thanks,
Paolo
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