linux-kernel - Re: CONFIG_PAGE_TABLE_ISOLATION=y on x86_64 causes gcc to segfault when building x86

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Message-ID: <alpine.DEB.2.20.1801031620020.1957@nanos>
Date:   Wed, 3 Jan 2018 16:21:32 +0100 (CET)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Lars Wendler <wendler.lars@....de>
cc:     LKML <linux-kernel@...r.kernel.org>, x86@...nel.org,
        Borislav Betkov <bp@...en8.de>,
        Andy Lutomirski <luto@...nel.org>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Greg KH <gregkh@...uxfoundation.org>
Subject: Re: CONFIG_PAGE_TABLE_ISOLATION=y on x86_64 causes gcc to segfault
 when building x86_32 binaries

On Wed, 3 Jan 2018, Lars Wendler wrote:
> Am Wed, 3 Jan 2018 13:05:38 +0100 (CET)
> schrieb Thomas Gleixner <tglx@...utronix.de>:
> > Also can you please try Linus v4.15-rc6 with PTI enabled so we can see
> > whether that's a backport issue or a general one?
> 
> Same problem with 4.15-rc6. So I suppose that means it's a general
> issue.

Just a shot in the dark as I just decoded another issue on a AMD CPU. Can
you please try the patch below?

Thanks,

	tglx

8<---------------

commit 52994c256df36fda9a715697431cba9daecb6b11
Author: Thomas Gleixner <tglx@...utronix.de>
Date:   Wed Jan 3 15:57:59 2018 +0100

    x86/pti: Make sure the user/kernel PTEs match
    
    Meelis reported that his K8 Athlon64 emits MCE warnings when PTI is
    enabled:
    
    [Hardware Error]: Error Addr: 0x0000ffff81e000e0
    [Hardware Error]: MC1 Error: L1 TLB multimatch.
    [Hardware Error]: cache level: L1, tx: INSN
    
    The address is in the entry area, which is mapped into kernel _AND_ user
    space. That's special because we switch CR3 while we are executing
    there.
    
    User mapping:
    0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd
    
    Kernel mapping:
    0xffffffff81000000-0xffffffff82000000          16M     ro         PSE         x  pmd
    
    So the K8 is complaining that the TLB entries differ. They differ in the
    GLB bit.
    
    Drop the GLB bit when installing the user shared mapping.
    
    Fixes: 6dc72c3cbca0 ("x86/mm/pti: Share entry text PMD")
    Reported-by: Meelis Roos <mroos@...ux.ee>
    Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
    Tested-by: Meelis Roos <mroos@...ux.ee>
    Cc: Borislav Petkov <bp@...en8.de>
    Cc: Tom Lendacky <thomas.lendacky@....com>
    Cc: stable@...r.kernel.org
    Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1801031407180.1957@nanos

diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c
index bce8aea65606..2da28ba97508 100644
--- a/arch/x86/mm/pti.c
+++ b/arch/x86/mm/pti.c
@@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(void)
 static void __init pti_clone_entry_text(void)
 {
 	pti_clone_pmds((unsigned long) __entry_text_start,
-			(unsigned long) __irqentry_text_end, _PAGE_RW);
+			(unsigned long) __irqentry_text_end,
+		       _PAGE_RW | _PAGE_GLOBAL);
 }
 
 /*