linux-kernel - RE: [PATCH v2 1/4] dmaengine: xilinx

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Message-ID: <CY1PR02MB1692EB7A4E66BA30A8E0DB45DC130@CY1PR02MB1692.namprd02.prod.outlook.com>
Date:   Mon, 8 Jan 2018 10:52:01 +0000
From:   Appana Durga Kedareswara Rao <appanad@...inx.com>
To:     Vinod Koul <vinod.koul@...el.com>
CC:     "dan.j.williams@...el.com" <dan.j.williams@...el.com>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "lars@...afoo.de" <lars@...afoo.de>,
        "akinobu.mita@...il.com" <akinobu.mita@...il.com>,
        "joabreu@...opsys.com" <joabreu@...opsys.com>,
        "mike.looijmans@...ic.nl" <mike.looijmans@...ic.nl>,
        "kedare06@...il.com" <kedare06@...il.com>,
        "dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2 1/4] dmaengine: xilinx_dma: populate dma caps properly

Hi Vinod,

	Thanks for the review.... 
<Snip>
>> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct
>xilinx_dma_device *xdev,
>>  		chan->direction = DMA_MEM_TO_DEV;
>>  		chan->id = chan_id;
>>  		chan->tdest = chan_id;
>> +		xdev->common.directions = BIT(DMA_MEM_TO_DEV);
>>
>>  		chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
>>  		if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ -
>2415,6
>> +2416,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
>>  		chan->direction = DMA_DEV_TO_MEM;
>>  		chan->id = chan_id;
>>  		chan->tdest = chan_id - xdev->nr_channels;
>> +		xdev->common.directions |= BIT(DMA_DEV_TO_MEM);
>>
>>  		chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
>>  		if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { @@ -
>2629,6
>> +2631,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
>>  		dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
>>  	}
>>
>> +	xdev->common.dst_addr_widths = BIT(addr_width / 8);
>> +	xdev->common.src_addr_widths = BIT(addr_width / 8);
>
>Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers? What is value
>of addr_width here typically? Usually controllers can support different widths and
>this is a surprise that you support only one value

Controller supports address width of 32 and 64.
addr_width typical values are 32-bit or 64-bit .
Here addr_width is device-tree parameter...
my understanding of src_addr_widths/dst_addr_widths is, it is a bit mask of the 
address with in bytes that DMA supports, please correct if my understanding is wrong.

Regards,
Kedar.

>
>--
>~Vinod